參數(shù)資料
型號(hào): GS815118
廠商: GSI TECHNOLOGY
英文描述: 16Mb(1M x 18Bit) Sync Burst SRAM(16M位(1M x 18位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述: 16Mb的(100萬(wàn)x 18位)同步突發(fā)靜態(tài)存儲(chǔ)器(1,600位(100萬(wàn)× 18位)同步靜態(tài)隨機(jī)存儲(chǔ)器(帶2位脈沖地址計(jì)數(shù)器))
文件頁(yè)數(shù): 7/32頁(yè)
文件大?。?/td> 583K
代理商: GS815118
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
7/32
2000, Giga Semiconductor, Inc.
Preliminary
GS815118/36T-225/200/180/166/150/133
Mode Pin Functions
Note:
There areis a pull-up devices on the DP and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Check for Odd Parity
Check for Even Parity
Output Register Control
FT
H or NC
L or NC
Power Down Control
ZZ
H
ByteSafe Data Parity Control
DP
L
H or NC
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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