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參數(shù)資料
| 型號： | GS8151Z18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM) |
| 中文描述： | 16Mb的流水線和流量，通過同步唑的SRAM（1,600位流水線式和流通型同步唑靜態(tài)內存） |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 683K |
| 代理商： | GS8151Z18 |
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Rev: 1.01 1/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
1/27
2000, Giga Semiconductor, Inc.
Preliminary
GS8151Z18/36T-225/200/180/166/150/133
16Mb Pipelined and Flow Through
Synchronous NBT SRAM
225 MHz–133 MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
3.3 V-compatible inputs
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
Clock Control, registered, address, data, and control
ZZ pin for automatic power-down
JEDEC-standard 100-lead TQFP package
-225
-200
Pipeline
3-1-1-1
t
KQ
I
DD
410
375
Flow
Through
2-1-1-1
I
DD
255
235
Functional Description
The GS8151Z18/36T is a 16Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8151Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8151Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-180
5.5
3.2
340
8
10
235
-166
6
3.5
310
8.5
10
235
-150
6.6
3.8
290
10
10
235
-133
7.5
4.0
260
11
15
220
Unit
ns
ns
mA
ns
ns
mA
tCycle
4.4
2.5
5
3.0
t
KQ
tCycle
7.0
8.5
7.5
10
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
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| GS8152Z18 | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM) |
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| GS815V018AB-250 | 制造商:GSI Technology 功能描述:GS815V018AB-250 - Trays |
| GS815V018AB-250I | 制造商:GSI Technology 功能描述:GS815V018AB-250I - Trays |
| GS815V018AB-300 | 制造商:GSI Technology 功能描述:GS815V018AB-300 - Trays |
| GS815V018AB-300I | 制造商:GSI Technology 功能描述:GS815V018AB-300I - Trays |
| GS815V018AB-333 | 制造商:GSI Technology 功能描述:GS815V018AB-333 - Trays |
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