參數(shù)資料
型號： GS4910B
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 92/113頁
文件大?。?/td> 1017K
代理商： GS4910B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
92 of 113
A_Reference_Divide
(GS4911B only)
3Eh-3Dh
31-0
In the internal audio genlock block, this register defines
the denominator of the divide ratio.
This register may be programmed to manually genlock
the audio clock to the video clock.
The default value of this register will vary depending on
the output video standard selected.
Address 3Dh = bits 15-0
Address 3Eh = bits 31-16
Reference:
Section 3.6.2.2 on page 56
R/W
–
ACLK1_fs_Multiple
(GS4911B only)
3Fh
15-3
Reserved. Set these bits to zero when writing to 3Fh.
–
–
3Fh
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK1 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
ACLK2_fs_Multiple
(GS4911B only)
40h
15-3
Reserved. Set these bits to zero when writing to 40h.
–
–
40h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK2 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
ACLK3_fs_Multiple
(GS4911B only)
41h
15-3
Reserved. Set these bits to zero when writing to 41h.
–
–
41h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK3 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
RSVD
42h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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