參數(shù)資料
型號： GS4910B
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標清/圖形時鐘和定時發(fā)生器鎖相
文件頁數(shù)： 100/113頁
文件大?。?/td> 1017K
代理商： GS4910B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
100 of 113
V_Stop_2
5Fh
15
Reserved. Set this bit to zero when writing to 5Fh.
–
–
5Fh
14-0
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER2_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
Operator_Polarity_2
60h
15-4
Reserved. Set these bits to zero when writing to 60h.
–
–
60h
3
Polarity_2 - Use this bit to invert the polarity of the final
USER2 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference:
Section 3.8.3 on page 69
R/W
1
60h
2
AND_2 - logical operator: USER2_H AND USER2_V
Set this bit HIGH to output a signal that is only active
when both USER2_H and USER2_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference:
Section 3.8.3 on page 69
R/W
0
60h
1
OR_2 - logical operator: USER2_H OR USER2_V
Set this bit HIGH to output a signal that is active
whenever USER2_H or USER2_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference:
Section 3.8.3 on page 69
R/W
0
60h
0
XOR_2 - logical operator: USER2_H XOR USER2_V
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER2_H or USER2_V is active. Signal is inactive
when USER2_H and USER2_V are both active or both
inactive.
Reference:
Section 3.8.3 on page 69
R/W
0
H_Start_3
61h
15-0
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_3.
Reference:
Section 3.8.3 on page 69
R/W
0
H_Stop_3
62h
15-0
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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