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參數資料
| 型號： | GS1560A |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進程- R的第二雙率解串器 |
| 文件頁數： | 36/80頁 |
| 文件大小： | 842K |
| 代理商： | GS1560A |
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GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
36 of 80
In slave mode, the application layer fixes the center frequency of the reclocker such
that the lock algorithm will attempt to lock within the single data rate determined by
the setting of the SD/HD pin. Asynchronous lock times are also listed in the
Table
2-2: AC Electrical Characteristics
.
NOTE: The PCLK output will continue to operate during the lock detection process.
The frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin
is set LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.
For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED
output signal HIGH if (1) the reclocker has locked to the input data stream as
indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have
been correctly identified.
If after four attempts lock has not been achieved, the lock detection algorithm will
enter into PLL lock mode. In this mode, the reclocker will attempt to lock to the input
data stream without detecting SMPTE TRS or DVB-ASI sync words. This
unassisted process can take up to 10ms to achieve lock.
When reclocker lock as indicated by the internal pll_lock signal is achieved in this
mode, one of the following will occur:
1. In slave mode, data will be passed directly to the parallel outputs without any
further processing taking place and the LOCKED signal will be asserted HIGH
if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW; or
2. In master mode, the LOCKED signal will be asserted LOW, the parallel
outputs will be latched to logic LOW, and the SMPTE_BYPASS and DVB_ASI
output signals will also be set LOW.
3.6.2 Master Mode
Recall that the GS1560A/GS1561 is said to be in master mode when the
MASTER/SLAVE input signal is set HIGH. In this case, the following four device
pins become output status signals:
The combined setting of these pins will indicate whether the device has locked to
valid SMPTE or DVB-ASI data at SD or HD rates.
Table 3-2
shows the possible
combinations.
SMPTE_BYPASS
DVB_ASI
SD/HD
RC_BYP (GS1560A only)
相關PDF資料 |
PDF描述 |
|---|---|
| GS1560ACFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1561-CF | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1561-CFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1560ACF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1560ACFE3 | 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80 |
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