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參數(shù)資料
| 型號： | GS1560A |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進程- R的第二雙率解串器 |
| 文件頁數(shù)： | 31/80頁 |
| 文件大?。?/td> | 842K |
| 代理商： | GS1560A |
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GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
31 of 80
3.2 Serial Digital Input
The GS1560A/GS1561 contains two current mode differential serial digital input
buffers, allowing the device to be connected to two SMPTE 259M-C or 292M
compliant input signals.
Both input buffers have internal 50
Ω
termination resistors which are connected to
ground via the TERM1 and TERM2 pins. The input common mode level is set by
internal biasing resistors such that the serial digital input signals must be AC
coupled into the device. Gennum recommends using a capacitor value of 4.7uF to
accommodate pathological signals.
The input buffers use a separate power supply of +1.8V DC supplied via the
BUFF_VDD and PDBUFF_GND pins.
3.2.1 Input Signal Selection
A 2x1 input multiplexer is provided to allow the application layer to select between
the two serial digital input streams using a single external pin. When IP_SEL is set
HIGH, serial digital input 1 (DDI1 / DDI1) is selected as the input to the
GS1560A/GS1561's reclocker stage. When IP_SEL is set LOW, serial digital input
2 (DDI2 / DDI2) is selected.
3.2.2 Carrier Detect Input
For each of the differential inputs, an associated carrier detect input signal is
included, (CD1 and CD2). These signals are generated by Gennum's family of
automatic cable equalizers.
When LOW, CDx indicates that a valid serial digital data stream is being delivered
to the GS1560A/GS1561 by the equalizer. When HIGH, the serial digital input to
the device should be considered invalid. If no equalizer precedes the device, the
application layer should set CD1 and CD2 accordingly.
NOTE: If the GS1524 Automatic Cable Equalizer is used, the MUTE/CD output
signal from that device must be translated to TTL levels before passing to the
GS1560A/GS1561 CDx inputs. See
GS1560A Typical Application Circuit (Part A)
on page 73
for a recommended transistor network that will set the correct voltage
levels.
A 2x1 input multiplexer is also provided for these signals. The internal
carrier_detect signal is determined by the setting of the IP_SEL pin and is used by
the lock detect block of the GS1560A/GS1561 to determine the lock status of the
device, (see
Lock Detect on page 35
).
3.2.3 Single Input Configuration
If the application requires a single differential input, the second set of inputs may
be left unconnected. Tie the associated carrier detect pin HIGH, and leave the
termination pin unconnected.
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PDF描述 |
|---|---|
| GS1560ACFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1561-CF | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1561-CFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1560ACF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1560ACFE3 | 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80 |
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