- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384345 > GS1531 (Gennum Corporation) GS1531 HD-LINX-TM II Multi-Rate Serializer PDF資料下載
參數(shù)資料
| 型號： | GS1531 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| 中文描述： | GS1531的HD - LINX進程，商標(biāo)第二多速率串行器 |
| 文件頁數(shù)： | 8/49頁 |
| 文件大?。?/td> | 500K |
| 代理商： | GS1531 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
GS1531 Data Sheet
30573 - 4
July 2005
8 of 49
B8, F8, J8
IO_GND
–
Power
Ground connection for digital I/O buffers. Connect to digital GND.
C2
PD_VDD
–
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
C3
PD_GND
–
Power
Ground connection for the phase detector. Connect to analog GND.
D5
DVB_ASI
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the encoding of received
DVB-ASI data.
D6
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the device has
achieved lock in Data-Through mode.
It will be LOW otherwise.
E4
SD/HD
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set LOW, the device will be configured to transmit signal rates of
1.485Gb/s or 1.485/1.001Gb/s only.
When set HIGH, the device will be configured to transmit signal rates of
270Mb/s only.
E5, F5
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital GND.
E6, F6
CORE_VDD
–
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
F1
RSV
–
–
Connect to Analog GND.
F4
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input data bus width in SMPTE or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel input will be 20-bit demultiplexed data.
When set LOW, the parallel input will be 10-bit multiplexed data.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1531-CB | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| GS1531-CBE2 | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| GS1532 | HD-LINX II Voltage Controlled Oscillator |
| GS1560 | HD-LINX II Voltage Controlled Oscillator |
| GS9060 | HD-LINX II Voltage Controlled Oscillator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1531_08 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1531-CB | 制造商:Semtech Corporation 功能描述:Serializer 100-Pin BGA 制造商:Semtech Corporation 功能描述:HD/SD/ASI Transmitter |
| GS1531CBE2 | 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA |
| GS1531-CBE2 | 制造商:Gennum Corporation 功能描述:Serializer 100-Pin BGA |
| GS1531CBE3 | 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。