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參數(shù)資料
| 型號： | GS1531 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| 中文描述： | GS1531的HD - LINX進(jìn)程，商標(biāo)第二多速率串行器 |
| 文件頁數(shù)： | 10/49頁 |
| 文件大?。?/td> | 500K |
| 代理商： | GS1531 |
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GS1531 Data Sheet
30573 - 4
July 2005
10 of 49
G5
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the scrambling or encoding of
received SMPTE data. No I/O processing features will be available.
G6
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
impedance, including the
serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
G8
BLANK
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable input data blanking.
When set LOW, the luma and chroma input data is set to the appropriate
blanking levels. Horizontal and vertical ancillary spaces will also be set to
blanking levels.
When set HIGH, the luma and chroma input data pass through the device
unaltered.
H4
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select,
CS
, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
H5
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK. Command
and data read/write words are clocked into the device synchronously with
this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the host interface is not being used, tie this pin HIGH.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1531-CB | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| GS1531-CBE2 | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| GS1532 | HD-LINX II Voltage Controlled Oscillator |
| GS1560 | HD-LINX II Voltage Controlled Oscillator |
| GS9060 | HD-LINX II Voltage Controlled Oscillator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1531_08 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1531-CB | 制造商:Semtech Corporation 功能描述:Serializer 100-Pin BGA 制造商:Semtech Corporation 功能描述:HD/SD/ASI Transmitter |
| GS1531CBE2 | 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA |
| GS1531-CBE2 | 制造商:Gennum Corporation 功能描述:Serializer 100-Pin BGA |
| GS1531CBE3 | 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA |
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