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參數(shù)資料
| 型號： | GMS87C2020Q |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | MQFP-64 |
| 文件頁數(shù)： | 88/107頁 |
| 文件大?。?/td> | 1482K |
| 代理商： | GMS87C2020Q |
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HMS81C2012A/2020A
84
SEP. 2004 Ver 2.00
20. POWER FAIL PROCESSOR
The HMS81C20xxA has an on-chip power fail detection
circuitry to immunize against power noise. A configura-
tion register, PFDR, can enable or disable the power fail
detect circuitry. Whenever V
DD
falls close to or below
power fail voltage for 100ns, the power fail situation may
reset or freeze MCU according to PFDM bit of PFDR. Re-
fer to “7.4 DC Electrical Characteristics for Standard
Pins(5V)” on page 16.
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Note:
User can select power fail voltage level according to
PFD0, PFD1 bit of CONFIG register(703F
H
) at the OTP
(HMS87C20xxA) but
must select
the power fail voltage
level to define PFD option of “Mask Order & Verification
Sheet” at the mask chip(HMS81C20xxA).
Because the power fail voltage level of mask chip
(HMS81C20xxA) is determined according to mask option.
Note:
If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.
Table 20-1 Power fail processor
.
Figure 20-1 Power Fail Voltage Detector Register
Power FailFunction
OTP
MASK
Enable/Disable
PFDIS flag
PFDIS flag
Level Selection
PFS0 bit
PFS1 bit
Mask option
PFDM
7
6
5
4
3
2
1
0
PFS
INITIAL VALUE: ---- -100
B
ADDRESS: 0EF
H
PFDR
R/W
R/W
R/W
PFDIS
Operation Mode
0 : Normal operation regardless of power fail
1 : MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
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