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參數(shù)資料
| 型號： | GMS87C2020Q |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | MQFP-64 |
| 文件頁數(shù)： | 87/107頁 |
| 文件大?。?/td> | 1482K |
| 代理商： | GMS87C2020Q |
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HMS81C2012A/2020A
SEP. 2004 Ver 2.00
83
19. RESET
The HMS81C20xxA have two types of reset generation
procedures; one is an external reset input, the other is a
watch-dog timer reset. Table 19-1 shows on-chip hardware
initialization by reset action.
Table 19-1 Initializing Internal Status by Reset Action
19.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start ex-
ecution as shown in Figure 19-2.
Internal RAM is not affected by reset. When V
DD
is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at addresses FFFE
H
- FFFF
H
.
A connection for simple power-on-reset is shown in Figure
19-1.
Figure 19-1 Simple Power-on-Reset Circuit
Figure 19-2 Timing Diagram after RESET
19.2 Watchdog Timer Reset
Refer to “11. WATCHDOG TIMER” on page 42.
On-chip Hardware
Initial Value
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFF
H
) - (FFFE
H
)
Peripheral clock
Off
RAM page register
(RPR)
0
Watchdog timer
Disable
G-flag
(G)
0
Control registers
Refer to Table 8-1 on page 29
Operation mode
Main-frequency clock
Power fail detector
Disable
7036P
V
CC
10uF
+
10k
to the RESET pin
MAIN PROGRAM
Oscillator
(X
IN
pin)
FFFE FFFF
Stabilization Time
t
ST
= 62.5mS at 4.19MHz
RESET
ADDRESS
BUS
DATA
BUS
1
2
3
4
5
6
7
Start
FE
ADL
ADH
OP
RESET Process Step
~
~
~
~
~
~
t
ST
=
x 256
f
MAIN
÷
1024
1
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