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參數(shù)資料
| 型號(hào)： | GMS87C2020Q |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | MQFP-64 |
| 文件頁(yè)數(shù)： | 48/107頁(yè) |
| 文件大?。?/td> | 1482K |
| 代理商： | GMS87C2020Q |
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HMS81C2012A/2020A
44
SEP. 2004 Ver 2.00
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during re-
set and it should be set to “1” to operate after reset is re-
leased.
Example: Enables watchdog timer for Reset
:
LDM
:
:
CKCTLR,#xx1x_xxxxB;
WDTON
←
1
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit tim-
er by clearing bit5 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 7-bit timer interrupt set up.
LDM
LDM
CKCTLR,#xx0xxxxxB;
WDTON
←
0
WDTR,#7FH
;
WDTCL
←
1
:
Figure 11-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
T
WDTR
Interval of BIT
×
=
2
3
n
Source clock
BIT overflow
Binary-counter
WDTR
WDTIF interrupt
WDTR
←
"0100_0011
B
"
1
0
Match
Detect
Counter
Clear
1
2
3
0
3
WDT reset
reset
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