
GMS800 Series
viii
SEP. 2004
16-BIT operation
Bit Manipulation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
Flag
NVGBHIZC
1
ADDW dp
1D
2
5
16-Bits add without Carry
YA
←
( YA ) + ( dp +1 ) ( dp )
Compare YA contents with memory pair contents :
(YA)
(dp+1)(dp)
NV--H-ZC
2
CMPW dp
5D
2
4
N-----ZC
3
DECW dp
BD
2
6
Decrement memory pair
( dp+1)( dp)
←
( dp+1) ( dp) - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair
( dp+1) ( dp)
←
( dp+1) ( dp ) + 1
Load YA
YA
←
( dp +1 ) ( dp )
N-----Z-
5
LDYA dp
7D
2
5
N-----Z-
6
STYA dp
DD
2
5
Store YA
( dp +1 ) ( dp )
←
YA
--------
7
SUBW dp
3D
2
5
16-Bits subtract without carry
YA
←
( YA ) - ( dp +1) ( dp)
NV--H-ZC
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
Flag
NVGBHIZC
1
AND1 M.bit
8B
3
4
Bit AND C-flag : C
←
( C )
∧
( M .bit )
Bit AND C-flag and NOT : C
←
( C )
∧
~( M .bit )
Bit test A with memory :
Z
←
( A )
∧
( M ) , N
←
( M
7
) , V
←
( M
6
)
Clear bit : ( M.bit )
←
“0”
Clear A bit : ( A.bit )
←
“0”
Clear C-flag : C
←
“0”
Clear G-flag : G
←
“0”
Clear V-flag : V
←
“0”
Bit exclusive-OR C-flag : C
←
( C )
⊕
( M .bit )
Bit exclusive-OR C-flag and NOT : C
←
( C )
⊕
~(M .bit)
Load C-flag : C
←
( M .bit )
Load C-flag with NOT : C
←
~( M .bit )
Bit complement : ( M .bit )
←
~( M .bit )
Bit OR C-flag : C
←
( C )
∨
( M .bit )
Bit OR C-flag and NOT : C
←
( C )
∨
~( M .bit )
Set bit : ( M.bit )
←
“1”
Set A bit : ( A.bit )
←
“1”
Set C-flag : C
←
“1”
Set G-flag : G
←
“1”
Store C-flag : ( M .bit )
←
C
Test and clear bits with A :
A - ( M ) , ( M )
←
( M )
∧
~( A )
-------C
-------C
MM----Z-
2
AND1B M.bit
8B
3
4
3
BIT dp
0C
2
4
4
BIT !abs
1C
3
5
5
CLR1 dp.bit
y1
2
4
--------
--------
-------0
--0-----
-0--0---
-------C
-------C
-------C
-------C
--------
-------C
-------C
--------
--------
-------1
--1-----
--------
6
CLRA1 A.bit
2B
2
2
7
CLRC
20
1
2
8
CLRG
40
1
2
9
CLRV
80
1
2
10
EOR1 M.bit
AB
3
5
11
EOR1B M.bit
AB
3
5
12
LDC M.bit
CB
3
4
13
LDCB M.bit
CB
3
4
14
NOT1 M.bit
4B
3
5
15
OR1 M.bit
6B
3
5
16
OR1B M.bit
6B
3
5
17
SET1 dp.bit
x1
2
4
18
SETA1 A.bit
0B
2
2
19
SETC
A0
1
2
20
SETG
C0
1
2
21
STC M.bit
EB
3
6
22
TCLR1 !abs
5C
3
6
N-----Z-
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A - ( M ) , ( M )
←
( M )
∨
( A )
N-----Z-