參數(shù)資料
型號(hào)： GMS82524T
英文描述： [General Purpose(1) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 71/110頁(yè)
文件大小： 1980K
代理商： GMS82524T
GMS81508B/16B/24B, GMS82512/16/24
68
MAY. 2001 Ver 2.0
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 5 in
CKCTLR) to “1”. WDTON is initialized to “0” during re-
set and it should be set to “1” to operate after reset is re-
leased.
Example: Enables watchdog timer for Reset
:
LDM
:
:
CKCTLR,#xx1x_xxxxB;
WDTON
←
1
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 6-bit tim-
er by clearing bit5 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 6-bit timer interrupt set up.
LDM
LDM
CKCTLR,#xx0xxxxxB;
WDTON
←
0
WDTR,#7FH
;
WDTCL
←
1
:
Figure 17-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
LDM
LDM
CKCTLR,#3FH
WDTR,#04FH
;
Select 1/2048 clock source
,
WDTON
←
1, Clear Counter
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#04FH
;
Clear counter
WDTR,#04FH
;
Clear counter
WDTR,#04FH
;
Clear counter
Within WDT
detection time
Within WDT
detection time
T
WDTR
Interval of BIT
×
=
2
3
n
Source clock
BIT overflow
Binary-counter
WDTR
WDTIF interrupt
WDTR
←
“0100_0011
B
”
1
0
Match
Detect
Counter
Clear
1
2
3
0
3
WDT reset
reset
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