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| 型號： | GMS82524T |
| 英文描述： | [General Purpose(1) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 70/110頁 |
| 文件大小： | 1980K |
| 代理商： | GMS82524T |
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GMS81508B/16B/24B, GMS82512/16/24
MAY. 2001 Ver 2.0
67
17. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
Figure 17-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
Figure 17-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
Figure 17-2 WDTR: Watchdog Timer Data Register
to reset CPU
BASIC INTERVAL TIMER
OVERFLOW
Count source
enable
Watchdog
Counter (8-bit)
6-bit compare data
comparator
Watchdog Timer interrupt
clear
clear
WDTIF
WDTCL
“0”
“1”
WDTON in CKCTLR [0D3
H
]
Watchdog Timer
Register
WDTR
Internal bus line
6
[0E0
H
]
7
-
6
5
4
3
2
1
0
WDTCL
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
INITIAL VALUE: -011_1111
B
ADDRESS: 0E0
H
WDTR
W
W
W
W
6-bit compare data
W
W
W
W
NOTE:
The WDTON bit is in register CKCTLR.
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