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參數(shù)資料
| 型號(hào)： | GM72V66841ET-7K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, TSOP2-54 |
| 文件頁(yè)數(shù)： | 16/57頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | GM72V66841ET-7K |
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LG Semicon
GM72V66841CT/CLT
Mode Register Configuration
Burst read and SINGLE WRITE:
Data is only written to the column address
specified during the write cycle, regardless of the
burst length.
A7:
Keep this bit Low at the mode register set cycle.
A6, A5, A4: (LMODE):
These pins specify the CAS latency.
A3: (BT):
A burst type is specified . When full-page burst is
performed, only "sequential" can be selected.
A2, A1, A0: (BL):
These pins specify the burst length.
The mode register is set by the input to the
address pins (A0 to A13) during mode register
set cycles. The mode register consists of five
sections, each of which is assigned to address
pins.
A13, A12, A11, A10, A9, A8: (OPCODE):
The synchronous DRAM has two types of write
modes. One is the burst write mode, and the
other is the single write mode. These bits specify
write mode.
Burst read and BURST WRITE:
Burst write is performed for the specified burst
length starting from the column address specified
in the write cycle.
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A3
0
1
Burst Type
Sequential
Interleave
A6 A5 A4
0
0
0
0
0
1
0
1
0
0
1
1
CAS Latency
R
R
2
3
1
X
X
R
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst Length
BT=0
1
2
4
8
R
R
R
F.P.
BT=1
1
2
4
8
R
R
R
R
F.P. = Full Page
(512:GM72V66841CT/CLT)
R is Reserved (inhibit)
X: 0 or 1
15
A13 A12
Write mode
Burst read and BURST WRITE
R
Burst read and SINGLE WRITE
R
A13
0
A11 A10 A9
A8
A12
X
X
X
0
X
X
X
0
X
X
X
0
0
1
1
0
1
0
1
0
X
X
X
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