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參數(shù)資料
| 型號： | GM72V66841ELT-7J |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, TSOP2-54 |
| 文件頁數(shù)： | 37/57頁 |
| 文件大小： | 592K |
| 代理商： | GM72V66841ELT-7J |
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LG Semicon
GM72V66841CT/CLT
Refresh
Auto refresh:
All the banks must be Precharged before
executing an auto-refresh command. Since the
auto-refresh command updates the internal
counter every time it is executed and determines
the banks and the ROW addresses to be
refreshed, external address specification is not
required. The refresh cycle is 4,096 cycles/64ms.
(4,096 cycles are required to refresh all the ROW
addresses.) The output buffer becomes High-Z
after auto-refresh start. In addition, since a
Precharge has been completed by an internal
operation after the auto-refresh, an additional
Precharge operation by the Precharge command
is not required.
Self refresh:
After executing a self-refresh command, the self-
refresh operation continues while CKE is held
Low. During self-refresh operation, all ROW
addresses are refreshed by the internal refresh
timer. A self-refresh is terminated by a self-
refresh exit command. If you use distributed
auto-refresh mode with 15.6us interval in normal
read/write cycle, auto-refresh should be executed
within 15.6 us immediately after exiting from and
before entering into self refresh mode. If you use
address refresh or burst auto-refresh mode in
normal
read/write
cycle,
distributed auto-refresh with 15.6us interval
should be executed within 64 ms immediately
after exiting from and before entering into self
refresh mode.
4096
cycles
of
Others
Power down mode:
The synchronous DRAM enters Power down
mode when CKE goes Low in the IDLE state. In
Power down mode, Power consumption is
suppressed by deactivating the input initial
circuit. Power down mode continues while CKE
is held Low. In addition, by setting CKE to High,
the synchronous DRAM exits from the Power
down mode, and command input is enabled from
the next cycle. In this mode, internal refresh is
not performed.
Clock suspend (Active Power down) mode:
By driving CKE to Low during a bank-active or
read/write operation, the synchronous DRAM
enters Clock suspend mode. During Clock
suspend mode, external input signals are ignored
and the internal state is maintained. When CKE
is driven High, the synchronous DRAM
terminates Clock suspend mode, and command
input is enabled from the next cycle. For details,
refer to the "CKE Truth Table".
Power-up sequence:
During Power-up sequence, the DQM and the
CKE must be set to High. When 200
§á
has past
after Power on, all banks must be Precharged
using the Precharge command. After
t
RP
delay,
set 8 or more auto refresh commands. And set the
mode register set command to initialize the mode
register.
36
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PDF描述 |
|---|---|
| GM72V66841ELT-7K | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ELT-8 | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841Exx | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ELT-7 | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GM72V66841ELT-7K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ELT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
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