參數(shù)資料
型號(hào)： GE28F640W30T85
英文描述： EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述： 的EEPROM | FLASH動(dòng)畫(huà)| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù)： 45/91頁(yè)
文件大?。?/td> 994K
代理商： GE28F640W30T85
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
45
8.1
Read Mode (CR[15])
All partitions support two high-performance read configurations: synchronous burst mode and
asynchronous page mode (default). CR[15] sets the read configuration to one of these modes.
Status register, query, and identifier modes support only asynchronous and single-synchronous read
operations.
8.2
First Access Latency Count (CR[13:11])
The First Access Latency Count (CR[13:11]) configuration tells the device how many clocks must
elapse from ADV# de-assertion (V
IH
) before the first data word should be driven onto its data pins.
The input clock frequency determines this value. See
Table 13, “Configuration Register
Definitions” on page 44
for latency values.
Figure 15
shows data output latency from ADV#
assertion for different latencies.
NOTE:
Other First Access Latency Configuration settings are reserved.
Use these equations to calculate First Access Latency Count:
(1)
Clock Period (T) = 1 ÷ Frequency
(2)
Choose the number of CLK cycles,
n
, such that:
n × T
≥
t
AVQV +
t
ADD-DELAY
+ t
DATA
(3)
First Access Latency Count (LC) = n – 2
You must use LC = n - 1 when the starting address is
not
aligned to a 4-word boundary and
CR[3]=1 (no-wrap).
Figure 15. First Access Latency Configuration
Code 5
Code 4
Code 3
Code 2
Valid
Address
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Address [A]
ADV# [V]
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
相關(guān)PDF資料
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