參數(shù)資料
型號(hào): GE28F640W30T85
英文描述: EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述: 的EEPROM | FLASH動(dòng)畫(huà)| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù): 44/91頁(yè)
文件大?。?/td> 994K
代理商: GE28F640W30T85
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
44
Datasheet
Table 13. Configuration Register Definitions
Read
Mode
Res’d
First Access Latency
Count
WAIT
Polarity
Data
Output
Config
WAIT
Config
Burst
Seq
Clock
Config
Res’d
Res’d
Burst
Wrap
Burst Length
RM
R
LC2
LC1
LC0
WT
DOC
WC
BS
CC
R
R
BW
BL2
BL1
BL0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 14. Configuration Register Descriptions
Bit
Name
Description
Notes
1
15
RM
Read Mode
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
2
14
R
Reserved
5
13-11
LC2-0
First Access Latency
Count
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
10
WT
WAIT Signal Polarity
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
3
9
DOC
Data Output Configuration
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
8
WC
WAIT Configuration
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
7
BS
Burst Sequence
0 = Intel Burst Order
1 = Linear Burst Order (Default)
6
CC
Clock
Configuration
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
5
R
Reserved
5
4
R
Reserved
5
3
BW
Burst Wrap
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
2-0
BL2-0
Burst Length
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst (Available on the .13 μm lithography)
111 = Continuous Burst (Default)
4
NOTES:
1. Undocumented combinations of bits are reserved by Intel for future implementations.
2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status register and
configuration reads support single read cycles. CR[15]=1 disables configuration set by CR[14:0].
3. Data is not ready when WAIT is asserted.
4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.
5. Set all reserved configuration register bits to zero.
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