參數(shù)資料
型號： GCIXP1250-232
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 18/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-232
Intel
IXP1250 Network Processor
18
Datasheet
If the codes match, the data is free of errors and is sent.
If the codes don
’
t match, the missing or erroneous bits are determined through the code comparison
and the bit or bits are supplied or corrected.
ECC only corrects single bit errors. Multiple bit errors are detected, but not corrected.
No hardware attempt is made to correct the data that is still in storage. Eventually, it will be
overlaid by new data and, assuming the errors were transient, the incorrect bits will "go away."
There are no timing penalties associated with ECC operation.
2.5.5
SDRAM Configurations
2.5.6
SRAM Unit
The IXP1250 provides an SRAM Unit for very high bandwidth memory for storage of lookup
tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM
(up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and 2 Mbytes of SlowPort address space
for peripheral device access. The I/O signal timing is determined by internal address decodes and
configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes
an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for
atomic bit operations, and an 8 entry CAM for Read Locks.
The SRAM interface operates at one-half the IXP1250 Core frequency (0.5 * F
core
).
The SRAM Unit supports both Pipelined Burst Double Cycle Deselect (DCD) and Flowthru
SRAM types. Other SSRAM devices, including single cycle deselect, are not supported. The bus is
also used to attach BootROM and can be used to interface other peripheral devices such as custom
interface logic or MAC management ports. The SRAM interface provides three separate timing
domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort
access).
Table 6. SDRAM Configurations
Total
Memory
Number of
Chips
Size
DRAM
Configuration
(per bank)
Internal
Banks
Bank Bits
RAS Bits
CAS Bits
8 Mbytes
4
16 Mbit
512 K x 16-bit
2
1
11
8
16 Mbytes
8
16 Mbit
1 M x 8-bit
2
1
11
9
32 Mbytes
4
64 Mbit
2 M x 16-bit
2
1
13
8
64 Mbytes
8
64 Mbit
4 M x 8-bit
2
1
13
9
32 Mbytes
4
64 Mbit
1 M x 16-bit
4
2
12
8
64 Mbytes
8
64 Mbit
2 M x 8-bit
4
2
12
9
64 Mbytes
4
128 Mbit
2 M x 16-bit
4
2
12
9
128 Mbytes
8
128 Mbit
4 M x 8-bit
4
2
12
10
128 Mbytes
4
256 Mbit
4 M x 16-bit
4
2
13
9
256 Mbytes
8
256 Mbit
8 M x 8-bit
4
2
13
10
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