參數(shù)資料
型號(hào)： GCIXF440AC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 44/128頁
文件大?。?/td> 1262K
代理商： GCIXF440AC
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
44
Datasheet
3.2.4.2
GMII Management Data Register
Mnemonic: GMII_MNG_DAT
Address: 4CH
–
4DH (only in port 0)
In read mode, this register will get the value of the desired GMII management register. In write
mode, the desired management register will get the value of this register.
Note:
When CPU bus is in 8 bit mode, write access to this register must be done to both addresses,
starting at the low address.
GMIRY
1
GMII management access registers are ready.
This bit indicates whether the access to the GMII management registers had been
completed. During the access process, the value of this bit will be 0.
The bit will be set at the end of the process.
Writing to the GMII management access registers while this bit is cleared will be ignored,
although the crdy_l signal will be asserted.
AMAM
0
Automatic mdio access mode
Setting this bit will begin the Automatic access.
Note:
If the cpu bus is in 8-bit mode the automatic access will occur after a write access
to the high byte of the register.
Access Rules
Register
access
During GMII automatic access (GMIRY = 0) R, otherwise R/W.
Value after
reset
0003H
Bit Name
Bit #
Bit Description
Bit Name
Bit #
Bit Description
GMII_DT
15:0
GMII data.
Bit 15 is the most significant bit, corresponding to bit 15 of the accessed register. Bit 0 is
the least significant bit.
Access Rules
Register
access
Bits 12:2 , during GMII automatic access (GMII_MNG_ACC<GMIRY> = 0) R, otherwise
R/W
Bit 1 is always read only.
Value
after
reset
0000H
A4986-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GMII_DT
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參數(shù)描述
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