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參數(shù)資料
| 型號(hào)： | GCIXF440AC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 34/128頁(yè) |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF440AC |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
34
Datasheet
3.2.3.4
Transmit and Receive Parameters Register
Mnemonic: TX_RX_PARAM
Address: 26H
–
27H
The transmit and receive parameters register handles the control of the serial interface.
Bit Name
Bit #
Bit Description
CRC remove.
When set, the last four bytes of the received packet will not be transferred onto the IX Bus.
Packets shorter than 4 bytes will be discarded.
Header replay.
When set, packet header is transferred twice onto the IX Bus.
Header size.
Header size is used for the header replay function and for rxrdy signal assertion (even if the
header replay function is disabled). The header size is calculated in bytes as 4
×
HDRS
(HDRS > 4).
RESERVED
Additional flow control.
When this bit is asserted, the IXF1002 will send an additional flow-control packet if a
flow-control packet was sent upon assertion of the flct_{i} signal, and while this signal was
asserted, the link partner
’
s pause time period was about to end. This will cause the link
partner to receive the additional flow-control packet before its pause time counting ends.
NOTE:
This feature is operative only if XOND bit is equal to 0.
Single packet mode.
When set, a packet is loaded in the transmit FIFO only after the previous packet was
transmitted onto the serial line. When not set, the transmit FIFO can contain a maximum of
two packets.
XON disable.
When set, a flow-control packet with pause time equal to zero, will not be sent upon flct_{i}
signal deassertion.
Receive flow-control mode enable.
When set, transmission is paused upon receiving flow-control packets.
NOTE:
This bit is used only in GMII mode and in GPCS mode when Auto-Negotiation is
disabled (GMII_CTL<ANENBL=0>). In GPCS mode when Auto-Negotiation is
enabled, the desired mode should be written in the AN_ADV<PAUSE> bit, and the
final mode after the Auto-Negotiation will be reported in the GPCS_STT<RFC> bit.
CRC appending disable.
When set, packets are transmitted without padding or CRC appending to the end of the
packet. This field is ignored if the txasis signal is asserted during the start of packet loading.
NOTE:
In case of VLAN tag append, strip or replace, the frame check sequence (FCS)
field will be calculated by the IXF1002 (
see 4.2.2.1
).
Padding appending disable.
When set, short packets are transmitted without the addition of bytes complementing their
sizes to 64 bytes. When the CRCD bit is set, this bit is ignored. This field is ignored if the
txasis
signal is asserted during the start of packet loading.
CRCR
15
HRPL
14
HDRS
13:8
—
7:6
ADFC
5
SPM
4
XOND
3
RFLCE
2
CRCD
1
PADD
0
A4976-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
H
R
P
L
HDRS
A
D
F
C
S
P
M
X
O
N
D
C
R
C
R
P
A
D
D
C
R
C
D
R
F
L
C
E
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