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參數(shù)資料
| 型號： | GCIXF440AC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 125/128頁 |
| 文件大小： | 1262K |
| 代理商： | GCIXF440AC |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
125
Multi-Packet Mode
C
C.1
Overview
This addendum contains the description of a new Multi-Packet Mode of operation introduced for
the IXF1002 Dual Port Gigabit Ethernet Controller (GCIXF1002ED only).
C.2
Introduction - txrdy Assertion/Deassertion Rules
The IXF1002 uses a generic bus interface (IX Bus) for data transfer to and from its FIFOs. The
Transmit FIFO (TFIFO) is accessed according to a port selection signal (fps) as well as a transmit
enabling signal (txsel_l). When a data transfer occurs, it is synchronized to the main clock (clk),
and new data may be sent on each clock cycle. The IXF1002 provides a dedicated signal (txrdy),
which indicates that it is ready for data transfer into the TFIFO. The IXF1002 asserts the txrdy
signal when both of the following criteria are met:
The amount of free space in the TFIFO is greater than the predetermined FIFO transmit
threshold
(FFO_TSHD<TTH>).
The number of full packets stored in the TFIFO is less than two.
When the txrdy signal is asserted, the transfer burst size should be shorter than or equal to the FIFO
transmit threshold to ensure that there is adequate space in the TFIFO to store the data. The
IXF1002 allows transferring of up to one packet in a single data transfer burst.
Packet transmission across the IX Bus should continue until the amount of data sent is equal to the
FIFO transmit threshold or until the entire packet is transmitted into the TFIFO (i.e. EOP is
reached).
The IXF1002 deasserts txrdy to indicate at least one of the following:
The amount of free space in the TFIFO is below the FIFO transmit threshold
(FFO_TSHD<TTH>)
The number of full packets stored in the TFIFO is two
A data burst across the IX Bus is in progress
The FIFO transmit threshold value should be carefully selected based on latency, IX Bus data
transfer bandwidth, and frame sizes in order to avoid transmit underflow scenarios.
When a high serial transmit threshold value is programmed (TX_TSHD<TSD>), there may be
scenarios and systems when the IXF1002 limits the system performance from reaching full wire
speed bandwidth.This scenario mainly occurs when a small packet is transmitted between streams
of large packets. The cause of this performance degradation is related to the two packet maximum
in the TFIFO.
In order to overcome this problem, Multi-Packet Mode is introduced. In Multi-Packet Mode, the
maximum number of complete packets that can be stored in the TFIFO is sixteen instead of two.
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