參數(shù)資料
型號(hào)： FX839
英文描述： Analogue Control Interface
中文描述： 模擬控制接口
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 1138K
代理商： FX839
Analogue Control Interface
FX839
1997 Consumer Microcircuits Limited
7
D/839/4
1.5
General Description
The device comprises four groups of related functions: variable attenuators, digital to analogue converters, a
multiplexed analogue to digital converter with multiplexer, clock generator and four 8-bit magnitude
comparators with variable reference levels. These functions are all controlled by the 'C-BUS' serial interface
and are described below:
Variable Attenuators
The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled
independently.
Digital to Analogue Converters
Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this
mode the 'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the
DAC resolutions to be 10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes.
The upper and lower DAC reference voltages are defined internally as AV
DD
and V
SS
respectively. The output
voltage is expressed as:
V
OUT
= AV
DD
x (DATA / 2
n
) [Volts]
Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n
= 8 and binary code = 11111111 therefore DATA = 255
V
OUT
= AV
DD
x (255 / 256) [Volts]
Any one of the three DAC input latches may be loaded by sending an address/command byte followed by one
or two data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the
appropriate output.
When a DAC is disabled its output is defined as open-circuit.
Analogue to Digital Converter and ADC Clock Generator
A single successive approximation ADC is provided with four multiplexed inputs. In order to minimise the
sampling time of each input channel, a Sample and Hold circuit has not been included at the input of the ADC.
For the sampling to be accurate the input signal should not change significantly during the conversion time.
Since the typical application is for the monitoring of slowly changing control voltages this should not present
any problems. The maximum signal 'linear rate of change', 'S', can be quantified by the following expression
(for a maximum 1 bit error):
S = AV
DD
x f
adc_clk
/ (2
10
x 1000 x (10 + 2)) [mV/μs]
Where f
adc_clk
is the internal ADC clock frequency.
The programmable clock generator is intended to be flexible, making use of an external system clock signal or
a dedicated crystal. This clock signal is scaled to provide the internal ADC clock frequency (f
adc_clk
). The user
has full control of the frequency scaling factor and this should be chosen such that the input clock frequency, at
the XTAL/CLOCK pin, divided by this factor is no more than 1MHz.
相關(guān)PDF資料
PDF描述
FX856
FX919A 4-Level FSK Packet Data Modem
FXA1012 Frame Transfer CCD Image Sensor
FXA1012WC Frame Transfer CCD Image Sensor
FXC6000 Distributed Power Front-End
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FX839D2 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface
FX839D5 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface
FX839P4 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface
FX8-40P-SV(21) 制造商:Hirose 功能描述:CONN HEADER 40POS .6MM GOLD SMD
FX8-40P-SV(71) 功能描述:板對(duì)板與夾層連接器 40P STRT SMT HEADER BOARD VERTICAL TYPE RoHS:否 制造商:JAE Electronics 系列:WP3 產(chǎn)品類型:Receptacles 節(jié)距:0.4 mm 疊放高度:1 mm 安裝角: 位置/觸點(diǎn)數(shù)量:50 排數(shù):2 外殼材料:Plastic 觸點(diǎn)材料:Copper Alloy 觸點(diǎn)電鍍:Gold 電壓額定值:50 V 電流額定值:0.4 A
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*