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參數(shù)資料
| 型號： | FX839 |
| 英文描述： | Analogue Control Interface |
| 中文描述： | 模擬控制接口 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | FX839 |
Analogue Control Interface
FX839
1997 Consumer Microcircuits Limited
13
D/839/4
DAC CONTROL Register (Hex address $D3)
This register controls the resolution and the number of enabled DAC outputs:
NBIT DAC1, NBIT DAC2, NBIT DAC3
(Bit 7 to Bit 5)
These bits define the input resolutions for each of the four DACs. When 'NBIT
DACn is '0' the resolution of DACnis 8-Bits. When 'NBIT DACnis '1' the
resolution of DACn s 10-Bits.
Bit 4
Reserved for future use. This bit should be set to '0'.
DAC1 ENABLE, DAC2 ENABLE, DAC3 ENABLE
(Bit 3 to Bit 1)
These bits allow any one or more of the three DACs to be powered up. When '0'
the DACnis powered down and the output is high impedance. When '1' the DAC
is powered on and the output voltage is defined by the DAC Data Registers.
Bit 0
Reserved for future use. This bit should be set to '0'.
DAC1 DATA Register (Hex Address $D4)
DAC2 DATA Register (Hex Address $D5)
DAC3 DATA Register (Hex Address $D6)
The data in these three registers sets the analogue voltage at the output of DAC1, DAC2 and DAC3. This data
will consist of one or two bytes depending on the defined input resolution which is set by bits 7, 6 and 5 of the
DAC Control Register. When operating with 10-bit resolution Bit 7 to Bit 2 of the DACnDATA Register second
data byte must be set to "0".
ADC CONTROL Register (Hex Address $D7)
This register controls the resolution, active inputs and conversion modes of the ADC as described below:
Bit 7
Reserved for future use. This bit should be set to '0'.
Bit 6
Reserved for future use. This bit should be set to ‘1’.
(On reset, this bit is set to ‘0’).
READN
(Bit 5)
When this bit is set to '1' all active input channels are continuously sampled and
the latest converted data stored for each channel. When this bit is set to ‘0’ all
conversions are stopped so that they may be read.
ADC1 ACTIVE, ADC2 ACTIVE, ADC3 ACTIVE, ADC4 ACTIVE
(Bit 4 to Bit 1)
These bits allow any one or more of the four ADC input channels to be enabled.
When '0' the ADCINninput voltage is not converted. When '1' the ADCINninput
is defined as active and the input voltage is converted.
Note: ADC1 must always be enabled for any other channel to work.
(Bit 0)
Reserved for future use. This bit should be set to ‘0’.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FX839D2 | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface |
| FX839D5 | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface |
| FX839P4 | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Analogue Control Interface |
| FX8-40P-SV(21) | 制造商:Hirose 功能描述:CONN HEADER 40POS .6MM GOLD SMD |
| FX8-40P-SV(71) | 功能描述:板對板與夾層連接器 40P STRT SMT HEADER BOARD VERTICAL TYPE RoHS:否 制造商:JAE Electronics 系列:WP3 產(chǎn)品類型:Receptacles 節(jié)距:0.4 mm 疊放高度:1 mm 安裝角: 位置/觸點(diǎn)數(shù)量:50 排數(shù):2 外殼材料:Plastic 觸點(diǎn)材料:Copper Alloy 觸點(diǎn)電鍍:Gold 電壓額定值:50 V 電流額定值:0.4 A |
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