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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 17/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
17
1.4.
Host Interface
The host interface of the GMCH is optimized to support the Intel
Pentium
III
processor and Intel
Celeron
TM
processor in the FC-PGA package. The GMCH implements the host address, control, and data
bus interfaces within a single device. The GMCH supports a 4-deep in-order queue (i.e., supports
pipelining of up to 4 outstanding transaction requests on the host bus) . Host bus addresses are decoded
by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI
configuration space and Graphics memory. The GMCH takes advantage of the pipelined addressing
capability of the processor to improve the overall system performance.
The 82815 GMCH supports the 370-pin socket processor.
370-pin socket
(PGA370). The PGA370 is a zero insertion force (ZIF) socket that a processor in
the FC-PGA package will use to interface with a system board.
1.5.
System Memory Interface
The GMCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array.
The only DRAM type supported is industry standard Synchronous DRAM (SDRAM). The SDRAM
controller interface is fully configurable through a set of control registers.
The GMCH supports industry standard 64-bit wide DIMMs with SDRAM devices. The thirteen
multiplexed address lines (SMAA[12:0]) along with the two bank select lines (SBS[1:0]) allow the
GMCH to support 2M, 4M, 8M, 16M, and 32M x64 DIMMs. Only asymmetric addressing is supported.
The GMCH has 6 SCS# lines (2 copies of each for electrical loading), enabling the support of up to six
64-bit rows of SDRAM. The GMCH targets SDRAM with CL2 and CL3, and supports both single and
double-sided DIMMs. Additionally, the GMCH also provides a 1024 deep refresh queue. The GMCH
can be configured to keep up to 4 pages open within the memory array. Pages can be kept open in any
one bank of memory.
The Intel
815 chipset family supports up to 3 DIMM connectors in a system. A maximum of 2 double-
sided or 3 single-sided DIMMs may be populated when the SDRAM interface is operating at 133 MHz.
Upon detection that additional rows are populated beyond these configurations, the BIOS must down-
shift the SDRAM clocks to 100 MHz through a two-wire interface of the system clock generator.
SCKE[5:0] is used in configurations requiring powerdown mode for the SDRAM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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