
E
82371AB (PIIX4)
257
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Table 50. STD/SOff to On Timings
Sym
Parameter
Min
Max
Unit
Notes
t123
Resume Event to SUS[A:C]# Inactive
1
RTC
1
t124
SUS[A:C]# Inactive to Core Well Power Applied
0
ns
t125
Core Well Power Applied to PCI_STP# and CPU_STP# Float
0
ns
t126
Core Well Power Applied to PCI_RST# Active
0
ns
t127
Core Well Power Applied to CPURST Active
0
ns
t128
Core Well Power Applied to SLP# Inactive
0
ns
t129
Core Well Power Applied to STPCLK# Inactive
0
ns
t130
PCI_STP# and CPU_STP# Float to Clocks Running
2
t131
Core Well Power Applied to PWROK Active
1
ms
t132
PWROK Active to CPU_STP# and PCI_STP# Active
0
ns
t133
PCI_STP# and CPU_STP# Active to Clocks Stopped
2
PCICLK
3
t134
SUS[A:C]# Inactive to CPU_STP# and PCI_STP# Inactive
16
ms
t135
PWROK Active to CPU_STP# and PCI_STP# Inactive
1
RTC
1
t136
PCI_STP# and CPU_STP# Active to Clocks Running
1
2
PCICLK
3
t137
CPU_STP# and PCI_STP# Inactive to SUS_STAT[1:2]# Inactive
1
ms
t138
SUS_STAT[1:2]# Inactive to SUSCLK Running
1
RTC
1
t139
SUS_STAT[1:2]# Inactive to PCI_RST# Inactive
1
RTC
1
t140
SUS_STAT[1:2]# Inactive to CPU_STP# and PCI_STP# allowed to
change
2
RTC
1
t141
PCI_RST# Inactive to CPURST Inactive
1
RTC
1
NOTES:
1.
These signals are controlled off the internal RTC clock. 1 RTC is approximately 32 μs.
2.
There are no specific requirements for these timings related to PIIX4. The system manufacturer should
make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks
must be available and stable after time t136.
3.
See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.