
82371AB (PIIX4)
E
210
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
STPCLK#
Request to
CLKRUN
HCLK
ZZ
SUSTAT1#
CPU_STP
PCI bus
Stop Grant
Cycle
Request to
CLKRUN
7
1
3
4
5
8
stpclk.
NOTES:
The numbers shown in this figure are referenced in the bullets on previous page for entering and leaving the
Stop Clock State.
Figure 13. Stop Clock Example
11.2.3.
PCI CLOCK CONTROL
PIIX4 manages the PCI Clock Control through the CLKRUN# protocol as specified by the PCI Mobile Design
Guide Rev 1.0. PIIX4 acts as the CLKRUN# Central Resource
.
If the [CLKRUN_EN] bit is set in the Clock Control Register, PIIX4 requests to stop the PCI Clock if the bus has
been idle for 26 PCI Clocks. PIIX4 asserts the PCI CLKRUN# signal high for four clocks. If no other device in the
system denies the request to stop before the 5th PCI clock, then PIIX4 asserts the PCI_STP# signal to the clock
synthesizer to gate the PCI Clocks to the system.
PIIX4 should always receive a PCI clock even after the clocks have been stopped to the rest of the system. The
clock synthesizer must have one non-gated PCI clock signal routed to PIIX4. The clock synthesizer must follow
the timing diagrams shown in Figure 18 and Figure 19 for stopping and starting the PCI clocks.
11.3.
Peripheral Device Management
The PIIX4 Peripheral Device Management mechanisms provide means to detect an idle peripheral device and to
trap accesses to a peripheral device that has been powered down. Device activity can also reload the Global
Standby Timer or can generate a Clock Control Stop Break or Burst Event. Device Accesses (I/O or Memory)
are monitored from the PCI bus. For devices that sit on the ISA Bus, these accesses can be forwarded to the