參數(shù)資料
型號: FUSB1500MHX
廠商: Fairchild Semiconductor
文件頁數(shù): 4/15頁
文件大小: 0K
描述: IC USB 2.0 TRANSCEIVER 16-MLP
標準包裝: 3,000
類型: USB 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: USB 2.0
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-MLP(3x3)
包裝: 帶卷 (TR)
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB1500 Rev. 1.0.1
12
FUSB1500
/
FUSB1501
USB2.0
Full-Speed
/
Low-Speed
Transceiver
with
Charger
Detection
Functional Description (Continued)
Power Supply Configurations and Options
The three modes of power-supply operation are:
Normal Mode – The VIO and VREG3V3 pins are
connected. VIO is an independent voltage source
(1.65 to 3.6V) that is a function of the external
circuit configuration.
Disable Mode – VIO is not connected; VREG3V3 is
connected. In this mode, the D+, D- pins are three-
state and the device enters low-power (suspended)
state upon detection of VIO lost.
Hi-Z Mode – When the Hi-Z pin is pulled HIGH, with
VREG3V3 powered, the RCV/VP/VM interface can
be used to access the Baseband for production test
programming. VP/VM/RCV are in high impedance
states.
Sharing Mode – VIO is the only supply connected. In
this mode, the D+ and D- pins are three-state and
the FUSB1500 allows external signals up to 3.6V to
share the D+ and D- bus lines. Internally, the
circuitry limits leakage from the D+ and D- pins
(maximum 10
A) and V
IO such that device is in low-
power (suspended) state. The VP and VM pins are
driven HIGH and RCV is forced LOW as an
indication of this mode. Can be used for production
test programming via D+/D-. to UART or Baseband
processor. HiZ is to be Low or Floating to ensure
VP/VM/RCV is signaled to processor.
A summary of the supply configurations is described in
Table 5.
Table 5. Power Supply Mode Configuration Options
Pin
Hi-Z
Sharing
Disable
Normal
VREG3V3
3.3V Externally
Supplied
Not Connected
Connected
3.3V Externally Supplied
VIO
1.65 - 3.6V
Source
1.65-3.60V
Source
Not Connected
1.65V- 3.60V Source
VPU
Three-State (Off)
Function of Mode Set-up
D+, D-
Three-State
Function of Mode Set-up
VP / VM
Three-State
HIGH
Invalid
(23)
Function of Mode Set-up
RCV
Three-State
LOW
Invalid
(23)
Function of Mode Set-up
VPO, VMO,
SPEED_N,OE_N,
SUSPND, CONFIG
Inputs
Three-State
Function of Mode Set-up
HiZ
HIGH
LOW or Floating
Three-State
LOW or Floating
INT_N
HIGH
Three-State
Function of Mode Set-up
Note:
23. Three-state or driven LOW.
Single Ended Zero Detection Timing
The SE0 detection logic is activated when entering the
state “011” (SUSPND, CONFIG, and SPEED_N) and
the logic waits to detect an SE0 event. Since the
FUSB1500 can also be used as an LS host device, it is
important to ensure that the tLST time for the USB2.0
specification is met. tLST is the minimum time to not
interpret LS differential signaling as an SE0 and is
210ns in duration. Similarly for FS differential signaling,
there is a time period, tFST time, of 14ns.
Seeing an SE0 for greater than tLST results in the INT_N
pin toggling LOW. The FUSB1500 is designed for 260ns
(typical).
Exiting HiZ or Suspend Mode Timing
As the RCV path is required to maintain the previous
state through an SE0 event, there is the possibility when
exiting HiZ or Suspend Mode to have the previous result
stored. The transition through the SE0 decode logic is
such that software should ignore RCV for at least 100ns
when exiting HiZ mode to ensure the correct D+/D- state
is available on the RCV output.
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