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參數(shù)資料
型號: FT2232D-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 6/61頁
文件大?。?/td> 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓模塊: USB Introduction
標準包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動流量控制功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP
包裝: 標準包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
14
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
In addition to the BM chip features, the FT2232D incorporates the following new features and interface
modes:-
Enhanced Asynchronous Bit-Bang Interface: The FT2232D supports FTDIs BM chip Bit Bang mode. In
Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel
IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate
controlled by an internal time (equivalent to the baud rate prescaler). With the FT2232D device this mode
has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can
be used to allow external logic to be clocked by accesses to the Bit-Bang IO bus.
Synchronous Bit-Bang Interface: Synchronous Bit-Bang Mode differs from Asynchronous Bit-Bang mode
in that the device is only read when it is written to. Thus making it easier for the controlling program to
measure the response to an output stimulus as the data returned is synchronous to the output data.
High Output Drive Level Capability: The IO interface pins can be made to drive out at three times the
standard drive level thus allowing multiple devices, or devices that require a greater drive strength to be
interfaced to the FT2232D. This option is configured in the external EEPROM, ad can be set individually for
each channel.
Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.): The Multi-Protocol Synchronous
Serial Engine (MPSSE) interface is a new option designed to interface efficiently with synchronous serial
protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry
standards, or proprietary bus protocols. For instance, it is possible to connect one of the FT2232Ds
channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device
would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC
could use the MPSSE to download configuration data to the FPGA over USB. This data would define the
hardwares function on power up. The other FT2232 channel would be available for other devices. This
approach would allow a customer to create a “generic” USB peripheral, whose hardware function can be
defined under control of the application software. The FPGA based hardware could be easily upgraded or
totally changed simply by changing the FPGA configuration data file. (See FTDIs MORPH-IC development
module for a practical example, www.morph-ic.com )
MCU Host Bus Emulation: This new mode combines the A and B bus interface to make the FT2232D
interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU
families to be directly attached to the FT2232D with IO being performed over USB with the help of MPSSE
interface technology.
CPU-Style FIFO Interface: The CPU style FIFO interface is essentially the same function as the classic
FT245 interface; however the bus signals have been redefined to make them easier to interface to a CPU
bus.
Fast Opto-Isolated Serial Interface: A new proprietary FTDI protocol is designed to allow galvanically
isolated devices to communicate synchronously with the FT2232D using just 4 signal wires (over two dual
opto-isolators), and two power lines. The peripheral circuitry controls the data transfer rate in both
directions, whilst maintaining full data integrity. Maximum USB full speed data rates can be achieved. Both
A and B channels can communicate over the same 4 wire interface if desired.
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