參數(shù)資料
型號(hào)： FS6370-01G-XTP
廠商： ON Semiconductor
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL EEPROM 16SOIC
標(biāo)準(zhǔn)包裝： 3,000
類型： PLL 時(shí)鐘發(fā)生器
PLL： 是
輸入： 晶體
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 230MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
FS6370
9.0 Programming Information
Table 3: Register Map (Note: All register bits are cleared to zero on power-up)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 15
MUX_D2[1:0]
(selected via SEL_CD = 1)
MUX_C2[1:0]
(selected via SEL_CD = 1)
PDPOST_D
PDPOST_C
PDPOST_B
PDPOST_A
Byte 14
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
Byte 13
POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
Byte 12
POST_B[3:0]
POST_A[3:0]
Byte 11
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
LFTC_C2
(SEL_CD=1)
CP_C2
(SEL_CD=1)
FBKDIV_C2[10:8] M-Counter
(selected via SEL_CD pin = 1)
Byte 10
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
Byte 9
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
Byte 8
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
(SEL_CD=0)
CP_C1
(SEL_CD=0)
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD = 0)
Byte 7
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
Byte 6
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
Byte 5
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
Byte 4
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
Byte 3
REFDIV_B[7:0]
Byte 2
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
Byte 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
Byte 0
REFDIV_A[7:0]
9.1 Control Bit Assignments
If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output
frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time
constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
9.1.1. Power-Down
All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the
PD input is asserted. If the power-down bit contains a one, the related circuit will shut down if the PD pin is high (run mode only). When
the PD pin is low, power is enabled to all circuits.
If the power-down bit contains a zero, the related circuit will continue to function regardless of the PD pin state.
Rev. 3 | Page 12 of 28 | www.onsemi.com
相關(guān)PDF資料
PDF描述
FS6377-01IG-XTP IC CLOCK GEN PLL PROG 16SOIC
FS7145-02G-XTD IC CLOCK GEN PLL PROG 16SSOP
FSA221UMX IC SWITCH AUD USB DPDT 10-MLP
FSA8008AUMX IC CONFIG SW/AUD JACK DET 10UMLP
FSA8008UMX IC AUDIO JACK DETECTOR/SW 10UMLP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FS6377 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6377-01G-XTP 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*