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參數(shù)資料
| 型號(hào)： | FS6370-01G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL EEPROM 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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FS6370
Figure 5: FS6370 to FS6377
7.2 Non-Programming Migration Path
If the design has solidified on a particular EEPROM programming pattern, the EEPROM pattern can be hard-coded into a ROM-based
device. For high-volume requirements, a ROM-based device offers significant cost savings over the FS6370. Contact an ON
Semiconductor sales representative for more detail.
8.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to
be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and
STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but
the master device determines which mode is activated. A device that sends data onto the bus is defined as the
transmitter, and a device receiving data as the receiver.
I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of
VDD, while a logic-low corresponds to ground (VSS).
8.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable
whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START
or STOP condition. The following bus conditions are defined by the I2C-bus protocol.
8.1.1. Not Busy
Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
8.1.2. START Data Transfer
A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be
preceded by a START condition.
Rev. 3 | Page 8 of 28 | www.onsemi.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6377 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6377-01G-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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