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參數(shù)資料
| 型號： | FS6370-01G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL EEPROM 16SOIC |
| 標準包裝： | 3,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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FS6370
3.0 Functional Block Description
3.1 Phase Locked Loops (PLLs)
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a
desired frequency by a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop
filter, a voltage-controlled oscillator (VCO), and a feedback divider.
During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider.
The divider value is often referred to as the modulus, and is denoted as NR for the reference divider. The divided reference is fed into
the PFD.
The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise,
continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider
(the modulus is denoted by NF) to close the loop.
Figure 3: PLL Block Diagram
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
3.1.1. Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-
down frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2. Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a pre-scaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
For example, a fixed divide-by-eight pre-scaler could have been used in the feedback divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to
Rev. 3 | Page 3 of 28 | www.onsemi.com
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FS6377 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6377-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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