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參數(shù)資料
| 型號(hào)： | FS6370-01G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL EEPROM 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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FS6370
Table 13: AC Timing Specifications (Continued)
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Clock Output (PLL C clock via CLK_C pin)
Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs
active
100
45
Jitter, Long Term (
σ
y(τ))*
Tj(LT)
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs
active (A=50MHz, B=60MHz, D=14.318MHz)
40
105
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active
100
120
Jitter, Period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active
(A=50MHz, B=60MHz, D=14.318MHz)
40
440
ps
Clock Output (Crystal Oscillator via CLK_D pin)
Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
14.318
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs
active
14.318
20
Jitter, Long Term (
σ
y(τ))*
Tj(LT)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz,
C=40MHz)
14.318
40
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, no other PLLs active
14.318
90
Jitter, Period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz,
C=40MHz)
14.318
450
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Min.
Max.
Units
Clock frequency
fSCL
SCL
0
100
kHz
Bus free time between STOP and START
tBUF
4.7
μs
Set up time, START (repeated)
tsu:STA
4.7
μs
Hold time, START
thd:STA
4.0
μs
Set up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
μs
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
3.5
μs
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
μs
Low time, clock
tLO
SCL
4.7
μs
Set up time, STOP
tsu:STO
4.0
μs
Rev. 3 | Page 22 of 28 | www.onsemi.com
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| FS6377-01G-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6377-01G-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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