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參數(shù)資料
| 型號： | FPD33684B |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Power, Low EMI, TFT-LCD Column Driver with RSDS⑩ Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications |
| 中文描述： | 低功耗，低EMI，TFT - LCD的柱與⑩輸入?yún)^(qū)特別職務隊，64 Grayshades，和384的XGA輸出驅動器/ SXGA應用 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 233K |
| 代理商： | FPD33684B |
Functional Description
(Continued)
R-DAC resistance values for the FPD33684B (designed to
match the gamma curve of the Samsung S6C0666) are
shown in
Figure 5
and
Figure 6
. Most applications will only
need to provide references for each of the two ends of the
two R-DACs (GMA1, GMA5, GMA6, and GMA10). Six addi-
tional, intemediate R-DAC tap points are available for further
customization.
CHARGE CONSERVATION TECHNOLOGY
National Semiconductor’s proprietary charge conservation
technology
significantly
reduces
Charge conservation works by briefly switching all of the
columns at the start of each line to a common node. This has
the effect of redistributing the charge stored in the capaci-
tance of the panel columns. Because half the columns are at
voltages more positive than V
and half are more nega-
tive, this redistribution of charge or “charge-sharing” has the
effect of pulling all of the columns to a neutral voltage near
the middle of the driver’s dynamic range. Thus, the voltages
on all the columns are driven approximately halfway toward
their next value with no power expended. This dramatically
reduces panel power dissipation (up to a theoretical limit of
50%) compared to conventional drivers which must drive
each column through the entire voltage swing every time
polarity is reversed.
’Smart’ charge sharing is used to further optimize this fea-
ture. Data inversion is monitored and charge shared only
across data ranges (when output polarity changes between
adjacent lines). This is useful during n-line inversion when
polarity changes do not occur at every line transition.
Charge sharing enables the FPD33684 to have faster output
rise and fall times than drivers with convential amplifiers.
This is due to the fact that the instantaneous currents sup-
plied by the energy stored in the panel are much higher than
the maximum output current of conventional drivers.
CSTIME
—
CHARGE SHARE TIME
The CSTIME pin allows the user to set the duration of
charge-sharing mode based on the panel capacitance and
resistance. The length of charge-sharing is important be-
cause it must be long enough to allow all of the columns to
equalize to the same value in order to achieve optimum
power performance. The length of charge-mode is user pro-
grammable. There are two common methods to drive the
CSTIME pin.
The first method is to actively drive the CSTIME input with a
control signal. This may be achieved by connecting the
LOAD signal to the CSTIME input.The width of the
LOAD/CSTIME signal determines the amount of time spent
in charge-sharing. This width may be optimized for a particu-
lar panel load. A ’typical’ width is 800ns. If desired, the
CSTIME pin may be driven independently, however, this will
require an additional output from the timing controller.
At the rising edge of the CSTIME/LOAD input signal, the
outputs enter charge-sharing mode. Outputs remain in
charge-mode until the falling edge of the CSTIME/LOAD
signal.
A second method for setting charge-time is to connect a
resistor (R
) and capacitor (C
) in parallel be-
tween the CSTIME pin and ground. Only one resistor and
capacitor is required for the entire display. At the rising edge
of the LOAD signal, the CSTIME pin is internally pulled to
V
and then released (i.e. floated). At this time the outputs
enter charge-sharing mode. The voltage on the CSTIME pin,
power
consumption.
V
,will then decay toward GND at a rate determined by
the R
and C
time constant. When V
reaches V
/2 the output mode switches from charge shar-
ing to conventional amplifier drive mode. The charge-share
mode time can be calculated using the following equation:
t
charge-share
= 0.69 x R
CSTIME
x C
CSTIME
RSDS
DATA CHANNEL
The RSDS
data bus is comprised of nine differential data
pairs and a differential clock. The nine channels are orga-
nized as three busses of three channels each. Each three
channel bus corresponds on one of the three video colors,
red, green and blue. Because the clocking is dual edged, the
even fields of the 6-bit word are transmitted-received on a
first clock and are followed by the odd fields. One full pixel
(red, green, and blue subpixels) is transmitted every full
pixelclock cycle.
OPTIONAL LINE BUFFERS
The FPD33684 provides two general purpose, unity gain
output buffers, one located at each end of the input bank of
the die. These buffers may be used to repair an open column
line. The drive signal from the output of the faulted line can
be stitched to the input of the repair buffer during the repair
process. The output of the repair buffer is then routed to the
other side of the column line making it possible to maintain
fast rise and fall times on both ends of the afflicted column
line.
PIN DESCRIPTIONS
The pin order configuration for the FPD33684 is shown in
Figure 7
. Optional pins do not need to be carried off a
custom TCP or COF package but may require a connection
to a neighboring pad on the die by a tie on the tape.
CLKP and CLKN
—
DATA CLOCK (INPUT)
Differential clock input for RSDS
data loading.
D00P–D22N
—
RSDS
DATA BUS (INPUT)
D0xP–D0xN—Data for OUTPUTS 1,4,7...382 (red)
D1xP–D1xN—Data for OUTPUTS 2,5,8...383 (green)
D2xP–D2xN—Data for OUTPUTS 3,6,9...384 (blue)
Where x = 0 (LSB), 1 or 2 (MSB).
ENIO1/ENIO2
—
DATA LOADING ENABLE 1 AND 2 (I/O)
The ENIO1/ ENIO2 pins are used to daisy chain the
FPD33684 together with other FPD33684s. The first input in
the chain is normally connected to the SP signal (or it’s
equivalent) on the timing controller. If UP = H, then the
ENIO1 pin is configured as an input and the ENIO2 pin is
configured as an output. If UP = L, then the ENIO2 pin is
configured as an input and the ENIO1 pin is configured as an
output.
INVERT
—
DIGITAL DATA INVERT (INPUT)
When INVERT = H, RSDS data is inverted. The INVERT pin
can be tied either high or low through connection to a neigh-
boring pin, eliminating the need to bring the pin off the
package.
LOAD
—
DATA LOAD
(INPUT)
The rising edge of LOAD copies the digital video buffered by
the shift register into a second latch for conversion to analog.
The outputs are forced into charge share mode while load is
high. When CSTIME = LOAD the falling edge ends the
charge share time and the newly converted analog voltages
are driven by the outputs.
POL
—
POLARITY (INPUT)
F
www.national.com
8
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