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參數(shù)資料
| 型號： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大小： | 1535K |
| 代理商： | FMS7401 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
29
Bit 6 of the ADCNTRL2 register is the Programmable Comparator non-inverting input selection (COMPSEL) bit.
1
If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-
inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable Comparator
circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.
2
Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura-
tion enable bit. If VLOOP=0, the Programmable Comparator circuit is configured to compare the analog G4/AIN0 or G2/AIN2
input (COMPSEL=0 or 1) to one of the 63 voltage threshold levels. If VLOOP=1, enables the voltage loop configuration where
the analog G4/AIN0 or G2/AIN2 input (COMPSEL=0 or 1) to the Uncommitted (Error) Amplifier output (A
OUT
).
Bit 7 of the Digital Delay (DDELAY) register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0,
the Programmable Comparator circuit is disabled and the C
OUT
signal is low. If COMPEN=1, the Programmable Comparator
circuit is enabled and the C
OUT
signal generated by the comparison of the two inputs.
Bit 0 (COUT) of the Comparator Control (COMP) register is the latched comparator output (C
OUT
) signal. If the Programma-
ble Comparator circuit is enabled, the C
OUT
signal is latched by the main system instruction (F
ICLK
) clock into the COUT bit of
the COMP register. Software may only read the COUT bit to monitor the comparator’s activity. The COUT bit cannot cause
any microcontroller hardware interrupt or any other actions.
Figure 9. Programmable Comparator Block Diagram (VLOOP = 1)
V
REF
0.23R
R
+
_
+
_
ACH5
VLOOP
G7/A
OUT
G6/-A
IN
Programmable
Reference
C
OUT
COMP Register
Uncommitted (Error)
Amplifier
DIGITAL DELAY
CIRCUIT
3
2
1
0
PWMOFF (WKEN[6])
DD[3] DD[2] DD[1] DD[0]
DDELAY
Register
F
RCLK2
5
EPWM
En
Comparator
COMPSEL
(ADCNTRL2[6])
G4/AIN0
G2/AIN2
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