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參數(shù)資料
| 型號： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 15/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
15
1.
Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit.
2.
If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must
be set after the appropriate T
PLL_LOCK
wait time.
3.
Prior to entering Idle Mode, software must clear both FMODE and FSEL (the timer must be disabled in order to clear
either bit) keeping the PLLEN bit 1.
4.
Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit.
5.
Software may then instruct the device to enter Idle Mode.
6.
If all disabled circuits must be re-enabled after exiting from Idle Mode, repeat all initial steps enabling all circuits in the
appropriate order as well as waiting T
PLL_LOCK
.
1. Contact your local Fairchild Sales Representative for FMS7401 availability.
2. The MIW and Timer 0 Circuits are described later in the datasheet.
3. Refer to the
Electrical Characteristics
section of the datasheet for details.
4. Refer to the
Clock Circuit’s PLL
section of the datasheet for details.
5. The FSEL bit in the PSCALE register must be set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FMS7401L | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Digital Power Controller |
| FMS7401L_05 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Digital Power Controller |
| FMS7401LA_ABA3026U WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FMS7401LEM8X | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Digital Power Controller |
| FMS7401LEMT8X | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Digital Power Controller |
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