參數(shù)資料
型號: FM8P51EP
廠商: Electronic Theatre Controls, Inc.
英文描述: EPROM/ROM-Based 8-Bit Microcontroller
中文描述: 存儲器/基于ROM的8位微控制器
文件頁數(shù): 24/60頁
文件大?。?/td> 369K
代理商: FM8P51EP
FM8P51
Rev1.2 Mar 15, 2005
P.24/FM8P51
FEELING
TECHNOLOGY
timer interrupt flag to be set.
TABLE 2.1: Timer 1 Prescaler Rate
T1P1 : T1P0
0, 0
0, 1
1, 0
1, 1
FIGURE 2.5: Block Diagram of The Timer1
2.5 Timer2 & Timer3
Timer2 and Timer3 are two 8-bit incrementing timers, each with an 8-bit period register (PR2 and PR3, respectively)
and separate overflow interrupt flags. Timer2 and Timer3 can operate either as timers (increment on internal clock,
Fosc/4), or as counters (increment on falling edge of external clock on pin IOB0/T23CKI). They are also software
configurable to operate as a single 16-bit timer/counter. These timers are also used as the time base for the PWM
(Pulse Width Modulation) modules.
2.5.1 Timer2 & Timer3 in 8-Bit Mode
Both Timer2 and Timer3 will operate in 8-bit mode when the T16 (T23CON<4>) bit is clear. These two timers can be
independently configured to increment from the internal clock (Fosc/4), or from an external clock source on
IOB0/T23CKI pin. The timer clock source in configured by the TxCS bit (x = 2 for Timer2 (T23CON<0>), x = 3 for
Timer3 (T23CON<2>)). When TxCS is set, the clock source is the IOB0/T23CKI pin and the counters will increment
on every falling edge of the IOB0/T23CKI pin.
The timer increments from 00h until it equals the period register (PRx, x = 2 for Timer2, x = 3 for Timer3). It then
resets to 00h at the next increment cycle. The timer interrupt flag is set when the timer rollover to 00h. Timer2 and
Timer3 have individual interrupt flag bits (T2IF and T3IF).
Each timer also has a corresponding interrupt enable bit (T2IE and T3IE). The timer interrupt can be
enabled/disabled by setting/clearing this bit.
The timer s can be turned on and off under software control. When the timer on control bit (TxON, T23CON<1> and
T23CON<3>) is set, the timer increments from the clock source. When TxON is cleared, the timer is turned off and
cannot cause the timer interrupt flag to be set.
When TxCS is set, the clock source is the IOB0/T23CKI pin, and the counter will increment on every falling edge on
the IOB0/T23CKI pin. The T23CKI input is synchronized with internal phase clocks. This cause a delay from the
time a falling edge appears on T23CKI to the time TMR2 or TMR3 is actually incremented.
2.5.2 Timer2 & Timer3 in 16-bit Mode
To select 16-bit mode, set the T16 bit. In this mode, TMR2 and TMR3 are concatenated to from a 16-bit timer
(TMR3:TMR2). The 16-bit timer increments until it matches the 16-bit period register (PR3:PR2). On the following
timer clock, the timer value is reset to 0000h, and the T2IF bit is set.
When selecting the clock source for the 16-bit timer, the T2CS bit control the entire 16-bit timer and T3CS is a “don’t
Prescaler Rate
1 : 1
1 : 4
1 : 8
1 : 16
Fosc/4
Prescaler
1:1 to 1:16
T1P<1:0>
Comparator x8
TMR1
PR1
Equal
Reset
Set T1IF flag
Clock output
T1ON
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