參數(shù)資料
型號(hào): FM8P51
廠商: Electronic Theatre Controls, Inc.
英文描述: EPROM/ROM-Based 8-Bit Microcontroller
中文描述: 存儲(chǔ)器/基于ROM的8位微控制器
文件頁(yè)數(shù): 48/60頁(yè)
文件大?。?/td> 369K
代理商: FM8P51
FM8P51
Rev1.2 Mar 15, 2005
P.48/FM8P51
FEELING
TECHNOLOGY
CLRA
Syntax:
Operands:
Operation:
Clear ACC
CLRA
None
00h
ACC;
1
Z
Z
The ACC register is cleared. Zero bit (Z) is set.
1
Status Affected:
Description:
Cycles:
CLRR
Syntax:
Operands:
Operation:
Clear R
CLRR R
0
R
63
00h
R;
1
Z
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
Status Affected:
Description:
Cycles:
CLRWDT
Syntax:
Operands:
Operation:
Clear Watchdog Timer
CLRWDT
None
00h
WDT;
00h
WDT prescaler (if assigned);
1
TO;
1
PD
TO,
PD
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
assigned to the WDT and not Timer0. Status bitsTO and
PD
are set.
1
Status Affected:
Description:
Cycles:
COMR
Syntax:
Operands:
Complement R
COMR R, d
0
R
63
d
[0,1]
R
dest
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Operation:
Status Affected:
Description:
Cycles:
DAA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Adjust ACC’s data format from HEX to DEC
DAA
None
ACC(hex)
ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition
operation and restored to ACC.
1
Cycles:
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