參數(shù)資料
型號: FDS6898A
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
中文描述: 9.4 A, 20 V, 0.014 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET
封裝: SO-8
文件頁數(shù): 2/5頁
文件大?。?/td> 81K
代理商: FDS6898A
FDS6898A Rev C (W)
Electrical Characteristics
Symbol
T
A
= 25°C unless otherwise noted
Test Conditions
Parameter
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
20
V
Breakdown Voltage Temperature
21
mV/
°
C
V
DS
= 16 V, V
GS
= 0 V
1
μ
A
nA
nA
I
GSSF
I
GSSR
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V
GS
= 12 V,
V
GS
= –12 V, V
DS
= 0 V
V
DS
= 0 V
100
–100
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
0.5
1
1.5
V
Gate Threshold Voltage
–3.5
mV/
°
C
V
GS
= 4.5 V, I
D
= 9.4 A
V
GS
= 2.5 V, I
D
= 8.3 A
V
GS
= 4.5 V, I
D
= 9.4 A,T
J
= 125
°
C
V
GS
= 4.5V,
V
DS
= 5 V
V
DS
= 5 V,
I
D
= 9.4 A
10
13
14
14
18
21
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
19
A
S
47
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
1821
440
208
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
10
15
34
16
16
3
4
20
27
55
29
23
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 9.4 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
1.3
1.2
A
V
V
GS
= 0 V,
I
S
= 1.3 A
(Note 2)
0.7
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 78°C/W when
mounted on a 0.5in
2
pad of 2 oz copper
b) 125°C/W when
mounted on a 0.02
in
pad of 2 oz
copper
c) 135°C/W when mounted on a
minimum mounting pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied
F
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