參數(shù)資料
型號: FDN338
廠商: Fairchild Semiconductor Corporation
英文描述: P-Channel Logic Level Enhancement Mode Field Effect Transistor
中文描述: P溝道增強(qiáng)模式的邏輯電平場效應(yīng)晶體管
文件頁數(shù): 2/4頁
文件大小: 85K
代理商: FDN338
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
BV
DSS
/
T
J
I
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 μA
I
D
= -250 μA, Referenced to 25
o
C
-20
V
Breakdown Voltage Temp. Coefficient
-28
mV/
o
C
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-1
μA
T
J
= 55°C
-10
μA
I
GSSF
I
GSSR
ON CHARACTERISTICS
(Note)
Gate - Body Leakage, Forward
V
GS
= 8 V,V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
100
nA
Gate - Body Leakage, Reverse
-100
nA
V
GS(th)
V
GS(th)
/
T
J
R
DS(ON)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 μA
I
D
= -250 μA, Referenced to 25
o
C
-0.4
-0.6
-1
V
Gate Threshold Voltage Temp. Coefficient
2
mV/
o
C
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= -1.6 A
0.115
0.13
T
J
=125°C
0.16
0.22
V
GS
= -2.5 V, I
D
= -1.3 A
V
GS
= -4.5 V, V
DS
= -5 V
V
DS
= -5 V, I
D
= -1.6 A
0.155
0.18
I
D(ON)
g
FS
DYNAMIC CHARACTERISTICS
On-State Drain Current
-2.5
A
Forward Transconductance
3
S
C
iss
C
oss
C
rss
SWITCHING CHARACTERISTICS
(Note)
Input Capacitance
V
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
405
pF
Output Capacitance
170
pF
Reverse Transfer Capacitance
45
pF
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Turn - On Delay Time
V
DD
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
6.5
13
ns
Turn - On Rise Time
20
35
ns
Turn - Off Delay Time
31
50
ns
Turn - Off Fall Time
21
35
ns
Total Gate Charge
V
DS
= -5 V, I
D
= -1.6 A,
V
GS
= -4.5 V
6
8.5
nC
Gate-Source Charge
0.8
nC
Gate-Drain Charge
1.3
nC
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
-0.42
A
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42 A
(Note)
-0.7
-1.2
V
Note:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Typical R
θ
JA
using the board layouts shown below on FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%.
FDN338P Rev.D
a. 250
0.02 in
o
C/W when mounted on a
2
pad of 2oz Cu.
b. 270
a 0.001 in
o
C/W when mounted on
2
pad of 2oz Cu.
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