參數(shù)資料
型號(hào): FDMW2512NZ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 小信號(hào)晶體管
英文描述: Monolithic Common Drain N-Channel 2.5V Specified PowerTrench MOSFET
中文描述: 7200 mA, 20 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: 2 X 5 MM, 0.80 MM HEIGHT, MicroFET, MLP-6
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 139K
代理商: FDMW2512NZ
FDMW2512NZ Rev D
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
V
GS
= 0 V,
I
D
= 250
μ
A
20
V
BV
DSS
T
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
I
D
= 250
μ
A, Referenced to 25
°
C
12
mV/
°
C
V
DS
= 16 V,
V
GS
=
±
12 V,
V
GS
= 0 V
V
DS
= 0 V
1
μ
A
μ
A
±
10
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= 250
μ
A, Referenced to 25 C
V
GS
= 4.5 V,
I
D
= 7.2 A
V
GS
= 4.0 V,
I
D
= 7.2 A
V
GS
= 3.1 V,
I
D
= 6.4 A
V
GS
= 2.5 V,
I
D
= 6.4 A
V
GS
= 4.5 V, I
D
= 7.2 A, T
J
=125
°
C
V
DS
= 5 V,
I
D
=7.2 A
I
D
= 250
μ
A
0.5
0.8
–3
1.5
V
mV/
°
C
19
20
22
23
25
30
26
28
32
34
39
m
g
FS
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
G
Gate Resistance
Forward Transconductance
S
740
165
127
1.4
pF
pF
pF
V
DS
= 15 V,
f = 1.0 MHz
V
GS
= 0 V,
f = 1.0 MHz
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
8
10
16
13
9
1
3
16
20
29
23
13
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 7.2 A,
Drain–Source Diode Characteristics
V
SD
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
V
GS
= 0 V,
I
S
= 1.8 A
(Note 2)
0.7
1.2
V
15
nS
Q
rr
Diode Reverse Recovery Charge
I
F
= 7.2 A,
dI
F
/dt = 100 A/μs
4
nC
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a)
55°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b) 145°C/W when mounted on a
minimum pad of 2 oz copper
Scale 1 : 1 on letter size paper
2
.
Pulse Test: Pulse Width < 300
μ
s,
Duty Cycle < 2.0%
3. The diode connected between the gate
and source serves only as protection
againts ESD. No gate overvoltage
rating is implied.
F
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