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參數(shù)資料
| 型號(hào)： | FDMF8704 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | MOSFETs |
| 英文描述： | High Current / High Frequency FET plus Driver Multi-chip Module |
| 中文描述： | 32 A HALF BRDG BASED MOSFET DRIVER, QCC56 |
| 封裝： | 8 X 8 MM, ROHS COMPLIANT, MO-220WLLD-5, MLP-56 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | FDMF8704 |
2
www.fairchildsemi.com
FDMF8704 Rev. F2
F
Pin Configuration
Pin Description
Pin
Name
Function
1, 6, 51, A
CGND
IC Ground. Ground return for driver IC.
2
HSEN
High Side FET Enable. Must be connected to BOOT pin.
3, 7, 52-54
NC
No connect
4
VCIN
IC Supply. +5V chip bias power. Bypass with a 1μF ceramic capacitor.
5
BOOT
Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor.
21, 40-50, C
VSWH
Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
8, 9, 11-20, B
VIN
Power Input. Output stage supply voltage.
10
TEST PAD 1
For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to
any pin.
22-38
PGND
Power ground. Output stage ground. Source pin of low side MOSFET(s).
39
TEST PAD 2
For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to
any pin.
55
DISB
Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low).
56
PWM
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Figure 2. MLP 8x8 56L Bottom View
PWM
DISB
NC
NC
NC
CGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
C
1
H
N
V
B
C
N
V
V
T
V
V
V
V
14
VIN
VIN
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
V
V
V
T
P
P
P
P
P
P
P
P
P
P
15
43
28
42
29
56
A
(CGND)
B
(VIN)
C
(VSWH)
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