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參數(shù)資料
| 型號(hào)： | FDFMC2P120 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | Integrated P-Channel PowerTrench MOSFET and Schottky Diode |
| 中文描述： | 3.5 A, 20 V, 0.2 ohm, P-CHANNEL, Si, POWER, MOSFET, MO-229WEEA |
| 封裝： | 3 X 3 MM, 0.80 MM HEIGHT, MLP-6 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | FDFMC2P120 |
FDFMC2P120 Rev.E (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
V
GS
= 0 V,
I
D
= –250
μ
A
–20
V
BV
DSS
T
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
I
D
= –250
μ
A, Referenced to 25
°
C
–11
mV/
°
C
V
DS
= –16 V,
V
GS
=
±
12 V,
V
GS
= 0 V
V
DS
= 0 V
–1
±
100
μ
A
nA
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
G,
I
D
= –250
μ
A, Referenced to 25
°
C
V
GS
= –4.5 V, I
D
= –2 A
V
GS
= –2.5 V, I
D
= –2 A
V
GS
= –4.5 V, I
D
= –2A,T
J
=125
°
C
V
GS
= –2.5 V, V
DS
= –5 V
V
DS
= –5 V,
I
D
= –3.5 A
I
D
= –250
μ
A
–0.6
–1.0
3
–1.5
V
mV/
°
C
101
145
136
6
125
200
180
m
I
D(on)
g
FS
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
G
Gate Resistance
On–State Drain Current
Forward Transconductance
–10
A
S
280
65
35
7
pF
pF
pF
V
DS
= –10 V, V
GS
= 0 V,
f = 1.0 MHz
V
GS
= 0 V,
f = 1.0 MHz
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
8
12
11
3.2
3
0.7
1
16
22
20
6.4
4
ns
ns
ns
ns
nC
nC
nC
V
DD
= –10 V,
V
GS
= –4.5 V, R
GEN
= 6
I
D
= –1 A,
V
DS
= –10 V, I
D
= –3.5 A,
V
GS
= –4.5 V
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
Q
rr
Diode Reverse Recovery Charge
–2
–1.2
A
V
V
GS
= 0 V,
I
S
= –2 A
(Note 2)
–0.9
13
3
nS
nC
I
F
= –3.5 A,
dI
F/
dt = 100 A/μs
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
are guaranteed by design while R
θ
JA
is determined by the user's board design.
(a).
R
θ
JA
= 60°C/W when mounted on a 1in
2
pad of 2 oz copper
(b).
R
θ
JA
= 145°C/W when mounted on a minimum pad of 2 oz copper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
F
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