參數(shù)資料
型號(hào): FC80960HA40SL2GW
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: CAP CER 3300PF 250V 10% X7R 0805
中文描述: 32-BIT, 40 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁(yè)數(shù): 40/102頁(yè)
文件大?。?/td> 828K
代理商: FC80960HA40SL2GW
80960HA/HD/HT
34
Advance Information
Datasheet
4.7
AC Specifications
Table 22. 80960Hx AC Characteristics (Sheet 1 of 2)
Per conditions in
Section 4.2, “Operating Conditions” on page 29
and
Section 4.7.1, “AC Test Conditions” on page 37
.
Symbol
Parameter
Min
Max
Units
Notes
Input Clock (1,7)
T
F
CLKIN Frequency
80960HA
80960HD
80960HT
16
16
16
40
40
25
MHz
MHz
MHz
T
CLKIN Period
80960HA
80960HD
80960HT
25
25
40
62.5
62.5
62.5
ns
ns
ns
T
CS
CLKIN Period Stability
-250
+250
ps
(11)
T
CH
CLKIN High Time
8
ns
(11)
T
CL
CLKIN Low Time
80960HA
80960HD
80960HT
8
8
8
ns
ns
ns
(11)
T
CR
CLKIN Rise Time
0
4
ns
(11)
T
CF
CLKIN Fall Time
0
4
ns
(11)
Synchronous Outputs (1,2,3,6)
T
OV1
, T
OH1
Output Valid Delay and Output Hold for all
outputs except DT/R, BLAST and BREQ for
3.3 V and 5 V inputs and I/Os.
1.5
9.5
ns
T
OV2
, T
OH2
Output Valid Delay and Output Hold for DT/R
80960HA
80960HD
80960HT
T/2 + 1.5
3T/4 + 1.5
5T/6 + 1.5
T/2 + 9.5
3T/4 + 9.5
5T/6 + 9.5
ns
ns
ns
T
OV3
, T
OH3
Output Valid Delay and Output Hold for BLAST
1.5
9
ns
T
OV4
, T
OH4
Output Valid Delay and Output Hold for BREQ
0.5
9
ns
T
OV5
, T
OH5
Output Valid Delay and Output Hold for A3:2
1.5
8.5
T
OF
Output Float for all outputs
1.5
9
ns
(11)
Synchronous Inputs (1,7,8,9)
T
IS1
Input Setup for all inputs except
READY, BTERM,
HOLD, and BOFF
2.5
ns
T
IH1
Input Hold for all inputs except
READY, BTERM,
HOLD, and BOFF
2.5
ns
T
IS2
Input Setup for
READY, BTERM, HOLD, and
BOFF
6
ns
NOTE:
See
Table 23 “AC Characteristics Notes” on page 36
for all notes related to AC specifications.
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