參數資料
型號: FC80960HA40SL2GW
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: CAP CER 3300PF 250V 10% X7R 0805
中文描述: 32-BIT, 40 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數: 13/102頁
文件大小: 828K
代理商: FC80960HA40SL2GW
80960HA/HD/HT
Advance Information
Datasheet
7
3.1
Pin Descriptions
This section defines the 80960Hx pins.
Table 6
presents the legend for interpreting the pin
descriptions in
Table 7
. All pins float while the processor is in the ONCE mode, except TDO,
which can be driven active according to normal JTAG specifications.
Table 6.
Pin Description Nomenclature
Symbol
Description
I
Input only pin.
O
Output only pin.
I/O
Pin can be input or output.
-
Pin must be connected as indicated for proper device functionality.
S(E)
Synchronous edge sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
S(L)
Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
A(E)
Asynchronous edge-sensitive input.
A(L)
Asynchronous level-sensitive input.
H(...)
While the processor bus is in the HOLD state (HOLDA asserted), the pin:
H(1) is driven to V
CC
H(0) is driven to V
SS
H(Z) floats
H(Q) continues to be a valid output
B(...)
While the processor is in the bus backoff state (BOFF asserted), the pin:
B(1) is driven to V
CC
B(0) is driven to V
SS
B(Z) floats
B(Q) continues to be a valid output
R(...)
While the processor’s RESET pin is asserted, the pin:
R(1) is driven to V
CC
R(0) is driven to V
SS
R(Z) floats
R(Q) continues to be a valid output
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