參數(shù)資料
型號: FAN53180
廠商: Fairchild Semiconductor Corporation
英文描述: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
中文描述: 6位VID控制2-4相DC - DC控制器
文件頁數(shù): 21/28頁
文件大?。?/td> 851K
代理商: FAN53180
PRODUCT SPECIFICATION
FAN53180
REV. 1.0.0 6/10/03
21
dissipation should be less than 400 mW. For our example,
with I
CC
= 7 mA, Q
GMF
= 24nC (max) and Q
GSF
= 31nC
(max), we find 202 mW in each driver, which is below the
400 mW dissipation limit. See the FAN53418 data sheet for
more details.
Ramp Resistor Selection
The ramp resistor (R
R
) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. The following expression is used for
determining the optimum value:
where A
R
is the internal ramp amplifier gain, A
D
is the
current balancing amplifier gain, R
DS
is the total low-side
MOSFET ON-resistance, and C
R
is the internal ramp capac-
itor value. A close standard 1% resistor value is 301k
.
The internal ramp voltage magnitude can be calculated
using:
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974 V.
Current Limit Set Point
To select the current limit set point, we need to find the resis-
tor value for R
LIM
. The current limit threshold for the
FAN53180 is set with a 3V source (V
LIM
) across R
LIM
with
a gain of 10.4mV/
μ
A (A
LIM
). R
LIM
can be found using the
following:
For values of R
LIM
greater than 500k
, the current limit may
be lower than expected, so some adjustment of R
LIM
may be
needed. Here, I
LIM
is the average current limit for the output
of the supply. For our example, choosing 120A for I
LIM
, we
find R
LIM
to be 200k
, for which we chose 200k
as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN53180, the maximum COMP voltage
(V
COMP(MAX)
) is 3.3 V, the COMP pin bias voltage (V
BIAS
)
is 1.2V, and the current balancing amplifier gain (A
D
) is 5.
Using V
R
of 0.765V, and R
DS(MAX)
of 5.95m
(low-side
ON-resistance at 125°C), we find a per-phase limit of
40.44A.
This limit can be adjusted by changing the ramp voltage V
R
.
But make sure not to set the per-phase limit lower than the
average per-phase current (I
LIM
/n).
There is also a per phase initial duty cycle limit determined
by:
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN53180 allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (R
O
). With the resistive output impedance,
the output voltage will droop in proportion with the load
current at any load current slew rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
R
R
A
L
×
DS
D
R
------------------------------------------------
=
(19)
R
R
----------------------------------------------------------
291k
=
=
V
R
A
--------------------------------------------------
1
D
R
(
)
×
V
SW
×
R
=
(20)
V
R
)
228kHz
1.5V
×
×
----------------------–
0.765V
=
=
V
RT
V
1
X
×
SW
R
O
----------------------–
--------------------------------------------------------------
=
(21)
R
LIM
A
LIM
V
O
×
-------------------------------
=
(22)
I
PHLIM
V
D
V
V
DS MAX
)
---------------------------------------------------------------------
I
R
2
----
(23)
D
MAX
D
V
-------------------------------------------------------
V
RT
×
=
(24)
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