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參數(shù)資料
| 型號(hào)： | EVAL-ADV739XFEZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 35/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV739XFEZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7403 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻解碼器 |
| 次要屬性： | 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板 |
| 已供物品： | 板 |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 32 of 108
Table 21. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x31
ED/HD Mode
Register 2
ED/HD pixel data valid
0
Pixel data valid off.
0x00
1
Pixel data valid on.
HD oversample rate select
0
4×.
1
2×.
ED/HD test pattern enable
0
HD test pattern off.
1
HD test pattern on.
ED/HD test pattern hatch/field
0
Hatch.
1
Field/frame.
ED/HD vertical blanking interval (VBI)
open
0
Disabled.
1
Enabled.
ED/HD undershoot limiter
0
Disabled.
0
1
11 IRE.
1
0
6 IRE.
1
1.5 IRE.
ED/HD sharpness filter
0
Disabled.
1
Enabled.
0x32
ED/HD Mode
Register 3
ED/HD Y delay with respect to the
falling edge of HSYNC
0
0 clock cycles.
0x00
0
1
One clock cycle.
0
1
0
Two clock cycles.
0
1
Three clock cycles.
1
0
Four clock cycles.
ED/HD color delay with respect to the
falling edge of HSYNC
0
0 clock cycles.
0
1
One clock cycle.
0
1
0
Two clock cycles.
0
1
Three clock cycles.
1
0
Four clock cycles.
ED/HD CGMS enable
0
Disabled.
1
Enabled.
ED/HD CGMS CRC enable
0
Disabled.
1
Enabled.
0x33
ED/HD Mode
Register 4
ED/HD Cr/Cb sequence
0
Cb after falling edge of HSYNC.
0x68
1
Cr after falling edge of HSYNC.
Reserved
0
0 must be written to this bit.
ED/HD input format
0
8-bit input.
1
Sinc compensation filter on DAC 1, DAC
2, DAC 3
0
Disabled.
1
Enabled.
Reserved
0
0 must be written to this bit.
ED/HD chroma SSAF filter
0
Disabled.
1
Enabled.
Reserved
1
1 must be written to this bit.
ED/HD double buffering
0
Disabled.
1
Enabled.
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
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