- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16539 > EVAL-ADV7180LQEBZ (Analog Devices Inc)BOARD EVALUATION ADV7180 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADV7180LQEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION ADV7180 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7180 |
| 主要屬性： | CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入 |
| 次要屬性： | 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7180BCPZ-REEL-ND - IC VIDEO DECODER SDTV 40-LFCSP ADV7180BSTZ-ND - IC VIDEO DECODER SDTV 64-LQFP ADV7180BCPZ-ND - IC VIDEO DECODER SDTV 40-LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
ADV7180
Data Sheet
Rev. I | Page 62 of 116
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
1. The user unmasks the CCAP interrupt mask bit (Register 0x50,
Bit 0, user sub map = 1). CCAP data occurs on the incoming
video. VDP slices CCAP data and places it into the VDP
readback registers.
2. The VDP CCAP available bit CC_CAP goes high, and the
VDP module signals to the interrupt controller to stimulate
an interrupt request (for CCAP in this case).
3. The user reads the interrupt status bits (user sub map) and
sees that new CCAP data is available (Register 0x4E, Bit 0,
user sub map = 1).
4. The user writes 1 to the CCAP interrupt clear bit (Register 0x4F,
Bit 0, user sub map = 1) in the interrupt I2C space (this is a
self-clearing bit). This clears the interrupt on the INTRQ
pin but does not have an effect in the VDP I2C area.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the
VDP_STATUS_CLEAR register, (Register 0x78, Bit 0,
user sub map = 1) to signify the CCAP data has been read
(therefore the VDP CCAP can be updated at the next
occurrence of CCAP).
7. The user goes back to Step 2.
Interrupt Mask Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
VDP_CCAPD_MSK, Address 0x50[0], User Sub Map
Setting VDP_CCAPD_MSK to 0 (default) disables the interrupt
on the VDP_CCAPD_Q signal.
Setting VDP_CCAPD_MSK to 1 enables the interrupt on the
VDP_CCAPD_Q signal.
VDP_CGMS_WSS_CHNGD_MSK, Address 0x50[2], User
Sub Map
Setting VDP_CGMS_WSS_CHNGD_MSK to 0 (default) disables
the interrupt on the VDP_CGMS_WSS_ CHNGD_Q signal.
Setting VDP_CGMS_WSS_CHNGD_MSK to 1 enables the
interrupt on the VDP_CGMS_WSS_CHNGD_Q signal.
VDP_GS_VPS_PDC_UTC_CHNG_MSK,
Address 0x50[4], User Sub Map
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 0 (default)
disables the interrupt on the
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 1 enables
the interrupt on the VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
VDP_VITC_MSK, Address 0x50[6], User Sub Map
Setting VDP_VITC_MSK to 0 (default) disables the interrupt
on the VDP_VITC_Q signal.
Setting VDP_VITC_MSK to 1 enables the interrupt on the
VDP_VITC_Q signal.
Interrupt Status Register Details
The following read-only bits contain data detection information
from the VDP module since the status bit is last cleared or
unmasked.
VDP_CCAPD_Q, Address 0x4E[0], User Sub Map
When VDP_CCAPD_Q is 0 (default), CCAP data is not
detected.
When VDP_CCAPD_Q is 1, CCAP data is detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E[2],
User Sub Map
When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or
WSS data is not detected.
When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data
is detected.
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E[4],
User Sub Map
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 0 (default),
Gemstar, PDC, UTC, or VPS data is not detected.
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 1, Gemstar,
PDC, UTC, or VPS data is detected.
VDP_VITC_Q, Address 0x4E[6], User Sub Map,
Read Only
When VDP_VITC_Q is 0 (default), VITC data is not detected.
When VDP_VITC_Q is 1, VITC data is detected.
Interrupt Status Clear Register Details
It is not necessary to write 0 to these write-only bits because
they automatically reset after they are set to 1 (self-clearing).
VDP_CCAPD_CLR, Address 0x4F[0], User Sub Map
Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],
User Sub Map
Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the
VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F[4], User Sub Map
Setting VDP_GS_VPS_PDC_UTC_CHNG_CLR to 1 clears the
VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR, Address 0x4F[6], User Sub Map
Setting VDP_VITC_CLR to 1 clears the VDP_VITC_Q bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| REC5-2415DRWZ/H4/A | CONV DC/DC 5W 9-36VIN +/-15VOUT |
| VI-J4R-EZ-S | CONVERTER MOD DC/DC 7.5V 25W |
| VE-B1P-EW | CONVERTER MOD DC/DC 13.8V 100W |
| GBC20DRTF | CONN EDGECARD 40POS DIP .100 SLD |
| DK-2612-02 | CABLE FIBER OPTIC DUAL ST-SC 2M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV7181CLFEBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Boxed Product (Development Kits) |
| EVAL-ADV7181CLQEBZ | 功能描述:BOARD EVAL FOR ADV7181CLQ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADV7181DEBZ | 功能描述:EVAL BOARD FOR ADV7181D RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADV7181EBM | 制造商:Analog Devices 功能描述:UNRELEASED EVAL BOARD I.C. - Bulk |
| EVAL-ADV7182EBZ | 功能描述:視頻 IC 開發(fā)工具 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評(píng)估:LMH1251 工作電源電壓:5 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。