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參數(shù)資料
| 型號： | EVAL-ADV7180LQEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION ADV7180 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7180 |
| 主要屬性： | CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入 |
| 次要屬性： | 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7180BCPZ-REEL-ND - IC VIDEO DECODER SDTV 40-LFCSP ADV7180BSTZ-ND - IC VIDEO DECODER SDTV 64-LQFP ADV7180BCPZ-ND - IC VIDEO DECODER SDTV 40-LFCSP |
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ADV7180
Data Sheet
Rev. I | Page 24 of 116
Timing Signals Output Enable
TIM_OE, Address 0x04[3]
The TIM_OE bit is regarded as an addition to the TOD bit. Setting
it high forces the output drivers for HS, VS, and FIELD into the
active state (that is, driving state) even if the TOD bit is set. If
TIM_OE is set to low, the HS, VS, and FIELD pins are three-
stated depending on the TOD bit. This functionality is beneficial if
the decoder is only used as a timing generator. This may be the
case if only the timing signals are extracted from an incoming
signal or if the part is in free-run mode, where a separate chip
can output a company logo, for example.
For more information on three-state control, see the Three-State
Output Drivers section and the Three-State LLC Driver section.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TIM_OE is 0 (default), HS, VS, and FIELD are three-
stated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all
the time.
Drive Strength Selection (Data)
DR_STR[1:0], Address 0xF4[5:4]
For EMC and crosstalk reasons, it may be desirable to strengthen or
weaken the drive strength of the output drivers. The DR_STR[1:0]
bits affect the P[15:0] for the 64-lead device or P[7:0] for the
48-lead, 40-lead, and 32-lead devices output drivers.
Note that DR_STR[1:0] also affects the drive strength of the
INTRQ interrupt pin on all ADV7180 models.
For more information on three-state control, see the Drive
(Sync) sections.
Table 16. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Drive Strength Selection (Clock)
DR_STR_C[1:0], Address 0xF4[3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
see the Drive Strength Selection (Sync) and the Drive Strength
Selection (Data) sections.
Table 17. DR_STR_C Function
DR_STR_C[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Drive Strength Selection (Sync)
DR_STR_S[1:0], Address 0xF4[1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, see the Drive Strength Selection
(Data) section.
Table 18. DR_STR_S Function
DR_STR_S[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN, Address 0x04[1]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock information
is presented on the SFL pin.
Polarity LLC Pin
PCLK, Address 0x37[0]
The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be necessary to
meet the setup-and-hold time expectations of follow-on chips.
When PCLK is 0, the LLC output polarity is inverted.
When PCLK is 1 (default), the LLC output polarity is normal
(see the Timing Specifications section).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV7181CLFEBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Boxed Product (Development Kits) |
| EVAL-ADV7181CLQEBZ | 功能描述:BOARD EVAL FOR ADV7181CLQ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADV7181DEBZ | 功能描述:EVAL BOARD FOR ADV7181D RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADV7181EBM | 制造商:Analog Devices 功能描述:UNRELEASED EVAL BOARD I.C. - Bulk |
| EVAL-ADV7182EBZ | 功能描述:視頻 IC 開發(fā)工具 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V |
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