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參數資料
| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 70/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關產品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 72 of 92
TIMER/COUNTER 0 AND TIMER/COUNTER 1 OPERATING MODES
The following sections describe the operating modes for
Timer/Counter 0 and Timer/Counter 1. Unless otherwise
noted, it should be assumed that these modes of operation are
the same for Timer 0 as for Timer 1.
MODE 0 (13-BIT TIMER/COUNTER)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 75 shows Mode 0 operation.
CORE
CLK*
CONTROL
P3.4/T0
GATE
P3.2/INT0
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
C/T = 0
C/T = 1
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
÷12
02987-
064
Figure 75. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. The overflow flag, TF0, can then be used to
request an interrupt. The counted input is enabled to the timer
when TR0 = 1 and either gate = 0 or INT0 = 1. Setting gate = 1
allows the timer to be controlled by external Input INT0 to
facilitate pulse width measurements. TR0 is a control bit in the
TCON SFR; gate is in TMOD. The 13-bit register consists of all
eight bits of TH0 and the lower five bits of TL0. The upper three
bits of TL0 are indeterminate and should be ignored. Setting the
run flag (TR0) does not clear the registers.
MODE 1 (16-BIT TIMER/COUNTER)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 76.
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
CORE
CLK*
CONTROL
P3.4/T0
GATE
P3.2/INT0
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
C/T = 0
C/T = 1
÷12
02987-
065
Figure 76. Timer/Counter 0, Mode 1
MODE 2 (8-BIT TIMER/COUNTER WITH
AUTORELOAD)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 77. Overflow from
TL0 not only sets TF0, but also reloads TL0 with the contents
of TH0, which is preset by software. The reload leaves TH0
unchanged.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
RELOAD
TH0
(8 BITS)
12
CORE
CLK *
P3.4/T0
GATE
TR0
C/T = 0
C/T = 1
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
02987-
066
P3.2/INT0
Figure 77. Timer/Counter 0, Mode 2
MODE 3 (TWO 8-BIT TIMER/COUNTERS)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 78.
TL0 uses the Timer 0 control bits: C/T, gate, TR0, INT0, and
TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1.
Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is
provided for applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can still be
used by the serial interface as a baud rate generator. It can be used
in any application not requiring an interrupt from Timer 1 itself.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
12
CORE
CLK*
P3.4/T0
GATE
P3.2/INT0
TR0
C/T = 0
C/T = 1
* CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
CORE
CLK/12
TF1
TH0
(8 BITS)
INTERRUPT
CORE
CLK/12
TR1
02987-
067
Figure 78. Timer/Counter 0, Mode 3
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